Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or
design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.

DOCUMENT NUMBER

9S12DT128BDGV1/D

MC9S12DT128B

Device User Guide

V01.07

Covers also

MC9S12DG128B, MC9S12DJ128B,

MC9S12DB128B

Original Release Date: 18 June 2001

Revised: 16 Aug 2002

Motorola, Inc

DOCUMENT NUMBER

9S12DT128BDGV1/D

Revision History

Version

Number

Revision

Date

Effective

Date

Author

Description of Changes

V01.00

18 Jun

2001

18 June

2001

Initial version (parent doc v2.03 dug for dp256).

V01.01

23 July

2001

23 July

2001

Updated version after review

V01.02

23 Sep

2001

23 Sep

2001

Changed Partname, added pierce mode, updated electrical
characteristics
some minor corrections

V01.03

12 Oct

2001

12 Oct

2001

Replaced Star12 by HCS12

V01.04

27 Feb

2002

27 Feb

2002

Updated electrical spec after MC-Qualification (IOL/IOH), Data for
Pierce, NVM reliability
New document numbering. Corrected Typos

V01.05

4 Mar

2002

4 Mar

2002

Increased VDD to 2.35V, removed min. oscillator startup
Removed Document order number except from Cover Sheet

V01.06

8 July

2002

22 July

2002

Added:
Pull-up columns to signal table,
example for PLL Filter calculation,
Thermal values for junction to board and package,
BGND pin pull-up
Part Order Information
Global Register Table
Chip Configuration Summary
Modified:
Reduced Wait and Run IDD values
Mode of Operation chapter
changed leakage current for ADC inputs down to +-1uA
Corrected:
Interrupt vector table enable register inconsistencies
PCB layout for 80QFP VREGEN position

V01.07

16 Aug

2002

16 Aug

2002

Minor corrections in table 1-1 & section 1.5.1

MC9S12DT128B Device User Guide -- V01.07

Table of Contents

Section 1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.1

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

1.2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

1.3

Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

1.4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

1.5

Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

1.5.1

Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

1.6

Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Section 2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

2.1

Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

2.2

Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

2.3

Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

2.3.1

EXTAL, XTAL -- Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

2.3.2

RESET -- External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

2.3.3

TEST -- Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

2.3.4

XFC -- PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

2.3.5

BKGD / TAGHI / MODC -- Background Debug, Tag High, and Mode Pin . . . . . . . .53

2.3.6

PAD[15] / AN1[7] / ETRIG1 -- Port AD Input Pin [15] . . . . . . . . . . . . . . . . . . . . . . . .54

2.3.7

PAD[14:8] / AN1[6:0] -- Port AD Input Pins [14:8]. . . . . . . . . . . . . . . . . . . . . . . . . . .54

2.3.8

PAD[7] / AN0[7] / ETRIG0 -- Port AD Input Pin [7] . . . . . . . . . . . . . . . . . . . . . . . . . .54

2.3.9

PAD[6:0] / AN0[6:0] -- Port AD Input Pins [6:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

2.3.10

PA[7:0] / ADDR[15:8] / DATA[15:8] -- Port A I/O Pins . . . . . . . . . . . . . . . . . . . . . . .54

2.3.11

PB[7:0] / ADDR[7:0] / DATA[7:0] -- Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . .54

2.3.12

PE7 / NOACC / XCLKS -- Port E I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

2.3.13

PE6 / MODB / IPIPE1 -- Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

2.3.14

PE5 / MODA / IPIPE0 -- Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

2.3.15

PE4 / ECLK -- Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

2.3.16

PE3 / LSTRB / TAGLO -- Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

2.3.17

PE2 / R/W -- Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

2.3.18

PE1 / IRQ -- Port E Input Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

2.3.19

PE0 / XIRQ -- Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

2.3.20

PH7 / KWH7 -- Port H I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

MC9S12DT128B Device User Guide -- V01.07

2.3.21

PH6 / KWH6 -- Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

2.3.22

PH5 / KWH5 -- Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

2.3.23

PH4 / KWH4 -- Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

2.3.24

PH3 / KWH3 / SS1 -- Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

2.3.25

PH2 / KWH2 / SCK1 -- Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

2.3.26

PH1 / KWH1 / MOSI1 -- Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

2.3.27

PH0 / KWH0 / MISO1 -- Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

2.3.28

PJ7 / KWJ7 / TXCAN4 / SCL -- PORT J I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . .57

2.3.29

PJ6 / KWJ6 / RXCAN4 / SDA -- PORT J I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . .58

2.3.30

PJ[1:0] / KWJ[1:0] -- Port J I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

2.3.31

PK7 / ECS / ROMCTL -- Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

2.3.32

PK[5:0] / XADDR[19:14] -- Port K I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

2.3.33

PM7 / BF_PSLM / TXCAN4 -- Port M I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

2.3.34

PM6 / BF_PERR / RXCAN4 -- Port M I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

2.3.35

PM5 / BF_PROK / TXCAN0 / TXCAN4 / SCK0 -- Port M I/O Pin 5 . . . . . . . . . . . . .58

2.3.36

PM4 / BF_PSYN / RXCAN0 / RXCAN4/ MOSI0 -- Port M I/O Pin 4 . . . . . . . . . . . . .59

2.3.37

PM3 / TX_BF / TXCAN1 / TXCAN0 / SS0 -- Port M I/O Pin 3 . . . . . . . . . . . . . . . . .59

2.3.38

PM2 / RX_BF / RXCAN1 / RXCAN0 / MISO0 -- Port M I/O Pin 2. . . . . . . . . . . . . . .59

2.3.39

PM1 / TXCAN0 / TXB -- Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

2.3.40

PM0 / RXCAN0 / RXB -- Port M I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

2.3.41

PP7 / KWP7 / PWM7 -- Port P I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

2.3.42

PP6 / KWP6 / PWM6 -- Port P I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

2.3.43

PP5 / KWP5 / PWM5 -- Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

2.3.44

PP4 / KWP4 / PWM4 -- Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

2.3.45

PP3 / KWP3 / PWM3 / SS1 -- Port P I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

2.3.46

PP2 / KWP2 / PWM2 / SCK1 -- Port P I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .60

2.3.47

PP1 / KWP1 / PWM1 / MOSI1 -- Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . .60

2.3.48

PP0 / KWP0 / PWM0 / MISO1 -- Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . .60

2.3.49

PS7 / SS0 -- Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

2.3.50

PS6 / SCK0 -- Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

2.3.51

PS5 / MOSI0 -- Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

2.3.52

PS4 / MISO0 -- Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

2.3.53

PS3 / TXD1 -- Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

2.3.54

PS2 / RXD1 -- Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

2.3.55

PS1 / TXD0 -- Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

2.3.56

PS0 / RXD0 -- Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

MC9S12DT128B Device User Guide -- V01.07

2.3.57

PT[7:0] / IOC[7:0] -- Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

2.4

Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

2.4.1

VDDX,VSSX -- Power & Ground Pins for I/O Drivers . . . . . . . . . . . . . . . . . . . . . . . .62

2.4.2

VDDR, VSSR -- Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator

2.4.3

VDD1, VDD2, VSS1, VSS2 -- Core Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

2.4.4

VDDA, VSSA -- Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . . . .63

2.4.5

VRH, VRL -- ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . .63

2.4.6

VDDPLL, VSSPLL -- Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . . . .63

2.4.7

VREGEN -- On Chip Voltage Regulator Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Section 3 System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.1

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Section 4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.1

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

4.2

Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

4.3

Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

4.3.1

Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

4.3.2

Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

4.3.3

Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

4.4

Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

4.4.1

Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

4.4.2

Pseudo Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

4.4.3

Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

4.4.4

Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Section 5 Resets and Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

5.1

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

5.2

Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

5.2.1

Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

5.3

Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

5.3.1

I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

5.3.2

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Section 6 HCS12 Core Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

MC9S12DT128B Device User Guide -- V01.07

Section 7 Clock and Reset Generator (CRG) Block Description . . . . . . . . . 75

7.1

Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

7.1.1

XCLKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Section 8 Enhanced Capture Timer (ECT) Block Description . . . . . . . . . . . . 75

Section 9 Analog to Digital Converter (ATD) Block Description. . . . . . . . . . 75

Section 10 Inter-IC Bus (IIC) Block Description . . . . . . . . . . . . . . . . . . . . . . . 75

Section 11 Serial Communications Interface (SCI) Block Description. . . . . 75

Section 12 Serial Peripheral Interface (SPI) Block Description . . . . . . . . . . 76

Section 13 J1850 (BDLC) Block Description. . . . . . . . . . . . . . . . . . . . . . . . . . 76

Section 14 Byteflight (BF) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . 76

Section 15 Pulse Width Modulator (PWM) Block Description . . . . . . . . . . . . 76

Section 16 Flash EEPROM 128K Block Description . . . . . . . . . . . . . . . . . . . 76

Section 17 EEPROM 2K Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Section 18 RAM Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Section 19 MSCAN Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Section 20 Port Integration Module (PIM) Block Description . . . . . . . . . . . . 77

Section 21 Voltage Regulator (VREG) Block Description . . . . . . . . . . . . . . . 77

Section 22 Printed Circuit Board Layout Proposal . . . . . . . . . . . . . . . . . . . . 78

Appendix A Electrical Characteristics

A.1

General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

A.1.1

Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

A.1.2

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

MC9S12DT128B Device User Guide -- V01.07

A.1.3

Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

A.1.4

Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

A.1.5

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

A.1.6

ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

A.1.7

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

A.1.8

Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

A.1.9

I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

A.1.10

Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

A.2

ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

A.2.1

ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

A.2.2

Factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

A.2.3

ATD accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

A.3

NVM, Flash and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

A.3.1

NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

A.3.2

NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

A.4

Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

A.5

Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

A.5.1

Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

A.5.2

Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

A.5.3

Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

A.6

MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

A.7

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

A.7.1

Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

A.7.2

Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

A.8

External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

A.8.1

General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

Appendix B Package Information

B.1

General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

B.2

112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

B.3

80-pin QFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

MC9S12DT128B Device User Guide -- V01.07

List of Figures

Figure 0-1

Order Partnumber Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 1-1

MC9S12DT128B Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 1-2

MC9S12DT128B Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 2-1

Pin assignments 112 LQFP for MC9S12DT128B,MC9S12DG128B,

MC9S12DJ128B, MC9S12DB128B48

Figure 2-2

Pin Assignments in 80 QFP for MC9S12DG128B, MC9S12DJ128B Bondout . .49

Figure 2-3

PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Figure 2-4

Colpitts Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 2-5

Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 2-6

External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 3-1

Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Figure 22-1 Recommended PCB Layout for 112LQFP Colpitts Oscillator . . . . . . . . . . . . . . .79

Figure 22-2 Recommended PCB Layout for 80QFP Colpitts Oscillator . . . . . . . . . . . . . . . . .80

Figure 22-3 Recommended PCB Layout for 112LQFP Pierce Oscillator . . . . . . . . . . . . . . . .81

Figure 22-4 Recommended PCB Layout for 80QFP Pierce Oscillator . . . . . . . . . . . . . . . . . .82

Figure A-1

ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure A-2

Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure A-3

Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure A-4

Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure A-5

SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure A-6

SPI Master Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure A-7

SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure A-8

SPI Slave Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure A-9

General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 22-5 112-pin LQFP mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . . . .120

MC9S12DT128B Device User Guide -- V01.07

List of Tables

Table 0-1

Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 0-2

Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 1-1

Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

$0000 - $000F

MEBI map 1 of 3 (Core User Guide) ........................................................22

$0010 - $0014

MMC map 1 of 4 (Core User Guide) ........................................................22

$0015 - $0016

INT map 1 of 2 (Core User Guide) ...........................................................23

$0017 - $0017

MMC map 2 of 4 (Core User Guide) ........................................................23

$0018 - $001B

Miscellaneous Peripherals (Device User Guide, Table 1-3) ....................23

$001C - $001D MMC map 3 of 4 (Core and Device User Guide, Table 1-4) ...................23

$001E - $001E MEBI map 2 of 3 (Core User Guide) ........................................................23

$001F - $001F

INT map 2 of 2 (Core User Guide) ...........................................................23

$0020 - $0027

Reserved ..................................................................................................24

$0028 - $002F

BKP (Core User Guide) ...........................................................................24

$0030 - $0031

MMC map 4 of 4 (Core User Guide) ........................................................24

$0032 - $0033

MEBI map 3 of 3 (Core User Guide) ........................................................24

$0034 - $003F

CRG (Clock and Reset Generator) ..........................................................25

$0040 - $007F

ECT (Enhanced Capture Timer 16 Bit 8 Channels) .................................25

$0080 - $009F

ATD0 (Analog to Digital Converter 10 Bit 8 Channel) ..............................28

$00A0 - $00C7 PWM (Pulse Width Modulator 8 Bit 8 Channel) .......................................29

$00C8 - $00CF SCI0 (Asynchronous Serial Interface) ......................................................31

$00D0 - $00D7 SCI1 (Asynchronous Serial Interface) ......................................................31

$00D8 - $00DF SPI0 (Serial Peripheral Interface) ............................................................32

$00E0 - $00E7 IIC (Inter IC Bus) ......................................................................................32

$00E8 - $00EF BDLC (Byte Level Data Link Controller J1850) ........................................33

$00F0 - $00F7

SPI1 (Serial Peripheral Interface) ............................................................33

$00F8 - $00FF Reserved ..................................................................................................33

$0100 - $010F

Flash Control Register (fts128k2) ............................................................34

$0110 - $011B

EEPROM Control Register (eets2k) ........................................................34

$011C - $011F Reserved for RAM Control Register ........................................................35

$0120 - $013F

ATD1 (Analog to Digital Converter 10 Bit 8 Channel) ..............................35

$0140 - $017F

CAN0 (Motorola Scalable CAN - MSCAN) ..............................................36

Table 1-2

Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . . . .37

$0180 - $01BF CAN1 (Motorola Scalable CAN - MSCAN) ..............................................38

MC9S12DT128B Device User Guide -- V01.07

$01C0 - $01FF Reserved ..................................................................................................39

$0200 - $023F

Reserved ..................................................................................................39

$0240 - $027F

PIM (Port Integration Module) ..................................................................40

$0280 - $02BF CAN4 (Motorola Scalable CAN - MSCAN) ..............................................42

$02C0 - $02FF Reserved ..................................................................................................43

$0300 - $035F

Byteflight ..................................................................................................43

$0360 - $03FF

Reserved ..................................................................................................45

Table 1-3

Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 1-4

Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 2-1

Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 2-2

MC9S12DT128B Power and Ground Connection Summary . . . . . . . . . . . . . . . . .61

Table 4-1

Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Table 4-2

Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Table 4-3

Voltage Regulator VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Table 5-1

Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Table 22-1 Suggested External Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Table A-1

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Table A-2

ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Table A-3

ESD and Latch-Up Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Table A-4

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Table A-5

Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Table A-6

5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Table A-7

Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Table A-8

ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Table A-9

ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Table A-10 ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Table A-11 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

Table A-12 NVM Reliability Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

Table A-13 Voltage Regulator Recommended Load Capacitances . . . . . . . . . . . . . . . . . . . .101

Table A-14 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

Table A-15 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

Table A-16 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

Table A-17 MSCAN Wake-up Pulse Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

Table A-18 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

Table A-19 SPI Slave Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

Table A-20 Expanded Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

MC9S12DT128B Device User Guide -- V01.07

Preface

The Device User Guide provides information about the MC9S12DT128B device made up of standard
HCS12 blocks and the HCS12 processor core.

This document is part of the customer documentation. A complete set of device manuals also includes the
HCS12 Core User Guide and all the individual Block User Guides of the implemented modules. In a effort
to reduce redundancy all module specific information is located only in the respective Block User Guide.
If applicable, special implementation details of the module are given in the block description sections of
this document.

This document also covers the MC9S12DG128B, MC9S12DJ128B and MC9S12DB128B.

Table 0-1

shows the availability of peripheral modules on the various derivatives. For details about the

compatibility within the MC9S12D-Family refer also to engineering bulletin EB386.

Table 0-1 Derivative Differences

NOTES

: Available for this device,

: Not available for this device

Modules

MC9S12DT128B

MC9S12DG128B

MC9S12DJ128B

MC9S12DB128B

# of CANs

CAN4

CAN1

CAN0

J1850/BDLC

IIC

Byteflight

Package

112 LQFP

112 LQFP/80 QFP 112 LQFP/80 QFP

112 LQFP

Package

Code

PV/FU

Mask set

L85D

Temp Options

M, V, C

Notes

An errata exists

contact Sales

Office

An errata exists

contact Sales

Office

An errata exists

contact Sales

Office

An errata exists

contact Sales

Office

MC9S12DT128B Device User Guide -- V01.07

The following figure provides an ordering number example for the MC9S12D128B devices.

Figure 0-1 Order Partnumber Example

See

Table 0-2

for names and versions of the referenced documents throughout the Device User Guide.

Table 0-2 Document References

User Guide

Version

Document Order Number

HCS12_V1.5 Core User Guide

1.2

HCS12COREUG

Clock and Reset Generator (CRG) Block User Guide

V03

S12CRGV3/D

Enhanced Capture Timer 16 Bit 8 Channel (ECT_16B8C) Block User Guide

V01

S12ECT16B8CV1/D

Analog to Digital Converter 10 Bit 8 Channel (ATD_10B8C) Block User Guide

V02

S12ATD10B8CV2/D

Inter IC Bus (IIC) Block User Guide

V02

S12IICV2/D

Asynchronous Serial Interface (SCI) Block User Guide

V02

S12SCIV2/D

Serial Peripheral Interface (SPI) Block User Guide

V02

S12SPIV2/D

Pulse Width Modulator 8 Bit 8 Channel (PWM_8B8C) Block User Guide

V01

S12PWM8B8CV1/D

128K Byte Flash (FTS128K) Block User Guide

V01

S12FTS128KV1/D

2K Byte EEPROM (EETS2K) Block User Guide

V01

S12EETS2KV1/D

Byte Level Data Link Controller -J1850 (BDLC) Block User Guide

V01

S12BDLCV1/D

Motorola Scalable CAN (MSCAN) Block User Guide

V02

S12MSCANV2/D

Voltage Regulator (VREG) Block User Guide

V01

S12VREGV1/D

Port Integration Module (PIM_9DT128) Block User Guide

V01

S12PIMDT128V1/D

Byteflight (BF) Block User Guide

V01

S12BFV1/D

MC9S12 DJ128B C FU

Package Option

Temperature Option

Device Title

Controller Family

Temperature Options

C = -40°C to

85°C

V = -40°C to 105°C
M = -40°C to 125°C

Package Options

FU =

80QFP

PV = 112LQFP

MC9S12DT128B Device User Guide -- V01.07

Section 1 Introduction

1.1 Overview

The MC9S12DT128B microcontroller unit (MCU) is a 16-bit device composed of standard on-chip
peripherals including a 16-bit central processing unit (HCS12 CPU), 128K bytes of Flash EEPROM, 8K
bytes of RAM, 2K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), two
serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, two 8-channel, 10-bit
analog-to-digital converters (ADC), an 8-channel pulse-width modulator (PWM), a digital Byte Data Link
Controller (BDLC), 29 discrete digital I/O channels (Port A, Port B, Port K and Port E), 20 discrete digital
I/O lines with interrupt and wakeup capability, three CAN 2.0 A, B software compatible modules
(MSCAN12), a Byteflight module and an Inter-IC Bus. The MC9S12DT128B has full 16-bit data paths
throughout. However, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory
can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and
performance to be adjusted to suit operational requirements.

1.2 Features

HCS12 Core

16-bit HCS12 CPU

i. Upward compatible with M68HC11 instruction set

ii. Interrupt stacking and programmer's model identical to M68HC11

iii. 20-bit ALU

iv. Instruction queue

v. Enhanced indexed addressing

MEBI (Multiplexed External Bus Interface)

MMC (Module Mapping Control)

INT (Interrupt control)

BKP (Breakpoints)

BDM (Background Debug Mode)

CRG (Clock and Reset Generator)

Choice of low current Colpitts oscillator or standard Pierce Oscillator

PLL

COP watchdog

real time interrupt

clock monitor

8-bit and 4-bit ports with interrupt functionality

MC9S12DT128B Device User Guide -- V01.07

Digital filtering

Programmable rising or falling edge trigger

Memory

128K Flash EEPROM

2K byte EEPROM

8K byte RAM

Two 8-channel Analog-to-Digital Converters

10-bit resolution

External conversion trigger capability

Three 1M bit per second, CAN 2.0 A, B software compatible modules

Five receive and three transmit buffers

Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit

Four separate interrupt channels for Rx, Tx, error and wake-up

Low-pass filter wake-up function

Loop-back for self test operation

Enhanced Capture Timer

16-bit main counter with 7-bit prescaler

8 programmable input capture or output compare channels

Two 8-bit or one 16-bit pulse accumulators

8 PWM channels

Programmable period and duty cycle

8-bit 8-channel or 16-bit 4-channel

Separate control for each pulse width and duty cycle

Center-aligned or left-aligned outputs

Programmable clock select logic with a wide range of frequencies

Fast emergency shutdown input

Usable as interrupt inputs

Serial interfaces

Two asynchronous Serial Communications Interfaces (SCI)

Two Synchronous Serial Peripheral Interface (SPI)

Byteflight

Byte Data Link Controller (BDLC)

MC9S12DT128B Device User Guide -- V01.07

SAE J1850 Class B Data Communications Network Interface

Compatible and ISO Compatible for Low-Speed (<125 Kbps) Serial Data Communications in
Automotive Applications

Inter-IC Bus (IIC)

Compatible with I2C Bus standard

Multi-master operation

Software programmable for one of 256 different serial clock frequencies

112-Pin LQFP and 80-Pin QFP package options

I/O lines with 5V input and drive capability

5V A/D converter inputs

Operation at 50MHz equivalent to 25MHz Bus Speed

Development support

Single-wire background debugTM mode (BDM)

On-chip hardware breakpoints

1.3 Modes of Operation

User modes

Normal and Emulation Operating Modes

Normal Single-Chip Mode

Normal Expanded Wide Mode

Normal Expanded Narrow Mode

Emulation Expanded Wide Mode

Emulation Expanded Narrow Mode

Special Operating Modes

Special Single-Chip Mode with active Background Debug Mode

Special Test Mode (Motorola use only)

Special Peripheral Mode (Motorola use only)

Low power modes

Stop Mode

Pseudo Stop Mode

Wait Mode

MC9S12DT128B Device User Guide -- V01.07

Figure 1-1 MC9S12DT128B Block Diagram

128K Byte Flash EEPROM

8K Byte RAM

Enhanced Capture

RESET

EXTAL

XTAL

DD1,2

SS1,2

SCI0

2K Byte EEPROM

BKGD

R/W

MODB

XIRQ

NOACC/XCLKS

System

Integration

Module

(SIM)

VDDR

CPU12

Periodic Interrupt

COP Watchdog

Clock Monitor

Single-wire Background

Breakpoints

PLL

VSSPLL

XFC

VDDPLL

Multiplexed Address/Data Bus

VDDA

VSSA

VRH

VRL

ATD0

Multiplexed
Wide Bus

Multiplexed

DDX

SSX

Internal Logic 2.5V

Narrow Bus

PPAGE

DDPLL

SSPLL

PLL 2.5V

IRQ

LSTRB
ECLK
MODA

TEST

ADDR12

ADDR11

ADDR10

ADDR9

ADDR8

ADDR15

ADDR14

ADDR13

A12

A11

A10

A15

A14

A13

PB4

PB3

PB2

PB1

PB0

PB7

PB6

PB5

ADDR4

ADDR3

ADDR2

ADDR1

ADDR0

ADDR7

ADDR6

ADDR5

PE3
PE4
PE5
PE6
PE7

PE0
PE1
PE2

AN2

AN6

AN0

AN7

AN1

AN3
AN4
AN5

PAD03
PAD04
PAD05
PAD06

PAD07

PAD00

PAD01
PAD02

IOC2

IOC6

IOC0

IOC7

IOC1

IOC3
IOC4
IOC5

PT3
PT4
PT5

PT6

PT7

PT0

PT1
PT2

VRH
VRL

VDDA

VSSA

VRH

VRL

ATD1

AN2

AN6

AN0

AN7

AN1

AN3
AN4
AN5

PAD11
PAD12
PAD13
PAD14

PAD15

PAD08

PAD09
PAD10

VDDA
VSSA

RXD

TXD

MISO
MOSI

PS3
PS4
PS5

PS0
PS1
PS2

SCI1

RXD

TXD

PWM2

PWM6

PWM0

PWM7

PWM1

PWM3
PWM4
PWM5

PP3
PP4
PP5

PP6
PP7

PP0
PP1
PP2

PIX2

PIX0
PIX1

PIX3

ECS

PK3

PK7

PK0
PK1

XADDR17

ECS

XADDR14
XADDR15
XADDR16

SCK

PS6
PS7

SPI0

IIC

SDA

SCL

PJ6
PJ7

CAN0

RxCAN

TxCAN

PM1

PM0

CAN1

RxCAN

TxCAN

PM2
PM3
PM4
PM5
PM6
PM7

KWH2

KWH6

KWH0

KWH7

KWH1

KWH3

KWH4
KWH5

PH3
PH4
PH5

PH6

PH7

PH0

PH1

PH2

KWJ0
KWJ1

PJ0
PJ1

I/O Driver 5V

DDA

SSA

A/D Converter 5V &

DDRA

DDRB

PTA

PTB

DDRE

PTE

AD1

AD0

PTK

DDRK

PTT

DDRT

PTP

DDRP

PTS

DDRS

PTM

DDRM

PTH

DDRH

PTJ

DDRJ

PK2

BDLC

RxB

TxB

Clock and
Reset
Generation
Module

Voltage Regulator

VSSR

Debug Module

VDD1,2

VSS1,2

VREGEN

DDR

SSR

Voltage Regulator 5V & I/O

CAN4

RxCAN

TxCAN

MISO
MOSI

SCK

SPI1

PIX4

PIX5

PK4
PK5

XADDR18
XADDR19

Voltage Regulator Reference

KWP2

KWP6

KWP0

KWP7

KWP1

KWP3
KWP4
KWP5

KWJ6
KWJ7

Timer

(J1850)

Signals sho

wn in

Bold

are not a

v
ailab

le in the 80 Pin P

a
c
kage Option

Module to Port Routing

RX_BF

TX_BF

BYTE-

BF_PSYN

BF_PROK
BF_PERR

BF_PSLM

FLIGHT

MC9S12DT128B Device User Guide -- V01.07

1.5 Device Memory Map

Table 1-1

and

Figure 1-2

show the device memory map of the MC9S12DT128B after reset. Note that

after reset the EEPROM ($0000

$07FF) is hidden by the register space ($0000 - $03FF) and the RAM

($0000 - $1FFF). The bottom 1K Bytes of RAM ($0000 - $03FF) are hidden by the register space.

Table 1-1 Device Memory Map

Address

Module

Size

(Bytes)

$0000 $0017

CORE (Ports A, B, E, Modes, Inits, Test)

$0018 $0019

Reserved

$001A $001B Device ID register (PARTID)

$001C $001F CORE (MEMSIZ, IRQ, HPRIO)

$0020 $0027

Reserved

$0028 $002F

CORE (Background Debug Mode)

$0030 $0033

CORE (PPAGE, Port K)

$0034 $003F

Clock and Reset Generator (PLL, RTI, COP)

$0040 $007F

Enhanced Capture Timer 16-bit 8 channels

$0080 $009F

Analog to Digital Converter 10-bit 8 channels (ATD0)

$00A0 $00C7 Pulse Width Modulator 8-bit 8 channels (PWM)

$00C8 $00CF Serial Communications Interface (SCI0)

$00D0 $00D7 Serial Communications Interface (SCI1)

$00D8 $00DF Serial Peripheral Interface (SPI0)

$00E0 $00E7 Inter IC Bus

$00E8 $00EF Byte Level Data Link Controller (BDLC)

$00F0 $00F7

Serial Peripheral Interface (SPI1)

$00F8 $00FF

Reserved

$0100 $010F

Flash Control Register

$0110 $011B

EEPROM Control Register

$011C $011F Reserved

$0120 $013F

Analog to Digital Converter 10-bit 8 channels (ATD1)

$0140 $017F

Motorola Scalable CAN (CAN0)

$0180 $01BF

Motorola Scalable CAN (CAN1)

$01C0 $01FF Reserved

$0200 $023F

Reserved

$0240 $027F

Port Integration Module (PIM)

$0280 $02BF

Motorola Scalable CAN (CAN4)

$02C0 $02FF Reserved

$0300 $035F

Byteflight (BF)

$0360 $03FF

Reserved

160

$0000 $07FF

EEPROM array

2048

$0000 $1FFF

RAM array

8192

$4000 $7FFF

Fixed Flash EEPROM array
incl. 0.5K, 1K, 2K or 4K Protected Sector at start

16384

$8000 $BFFF Flash EEPROM Page Window

16384

MC9S12DT128B Device User Guide -- V01.07

Figure 1-2 MC9S12DT128B Memory Map

$C000 $FFFF

Fixed Flash EEPROM array
incl. 0.5K, 1K, 2K or 4K Protected Sector at end
and 256 bytes of Vector Space at $FF80

$FFFF

16384

Table 1-1 Device Memory Map

Address

Module

Size

(Bytes)

$0000

$FFFF

$C000

$8000

$4000

$0400
$0800
$1000
$2000

$FF00

EXT

NORMAL

SINGLE CHIP

EXPANDED

SPECIAL

SINGLE CHIP

VECTORS

$FF00

$FFFF

BDM
(If Active)

$C000

$FFFF

16K Fixed Flash EEPROM

2K, 4K, 8K or 16K Protected Boot Sector

$8000

$BFFF

16K Page Window
eight * 16K Flash EEPROM Pages

$4000

$7FFF

16K Fixed Flash EEPROM

0.5K, 1K, 2K or 4K Protected Sector

$2000

$3FFF

8K Bytes RAM

Mappable to any 8K Boundary

$0800

$0FFF

2K Bytes EEPROM

Mappable to any 2K Boundary

$0000

$03FF

1K Register Space

Mappable to any 2K Boundary

The address does not show the map after reset, but a useful map. After reset the map is:
$0000 $03FF: Register Space
$0000 $1FFF: 8K RAM
$0000 $07FF: 2K EEPROM (not visible)

MC9S12DT128B Device User Guide -- V01.07

1.5.1 Detailed Register Map

$0000 - $000F

MEBI map 1 of 3 (Core User Guide)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$0000

PORTA

Read:

Bit 7

Bit 0

Write:

$0001

PORTB

Read:

Bit 7

Bit 0

Write:

$0002

DDRA

Read:

Bit 7

Bit 0

Write:

$0003

DDRB

Read:

Bit 7

Bit 0

Write:

$0004

Reserved

Read:

Write:

$0005

Reserved

Read:

Write:

$0006

Reserved

Read:

Write:

$0007

Reserved

Read:

Write:

$0008

PORTE

Read:

Bit 7

Bit 1

Bit 0

Write:

$0009

DDRE

Read:

Bit 7

Bit 2

Write:

$000A

PEAR

Read:

NOACCE

PIPOE

NECLK

LSTRE

RDWE

Write:

$000B

MODE

Read:

MODC

MODB

MODA

IVIS

EMK

EME

Write:

$000C

PUCR

Read:

PUPKE

PUPEE

PUPBE

PUPAE

Write:

$000D

RDRIV

Read:

RDPK

RDPE

RDPB

RDPA

Write:

$000E

EBICTL

Read:

ESTR

Write:

$000F

Reserved

Read:

Write:

$0010 - $0014

MMC map 1 of 4 (Core User Guide)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$0010

INITRM

Read:

RAM15

RAM14

RAM13

RAM12

RAM11

RAMHAL

Write:

$0011

INITRG

Read:

REG14

REG13

REG12

REG11

Write:

$0012

INITEE

Read:

EE15

EE14

EE13

EE12

EEON

Write:

$0013

MISC

Read:

EXSTR1 EXSTR0 ROMHM

ROMON

Write:

$0014

MTST0

Test Only

Read:

Bit 7

Bit 0

Write:

MC9S12DT128B Device User Guide -- V01.07

$0015 - $0016

INT map 1 of 2 (Core User Guide)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$0015

ITCR

Read:

WRINT

ADR3

ADR2

ADR1

ADR0

Write:

$0016

ITEST

Read:

INTE

INTC

INTA

INT8

INT6

INT4

INT2

INT0

Write:

$0017 - $0017

MMC map 2 of 4 (Core User Guide)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$0017

MTST1

Test Only

Read:

Bit 7

Bit 0

Write:

$0018 - $001B

Miscellaneous Peripherals (Device User Guide, Table 1-3)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$0018

Reserved

Read:

Write:

$0019

Reserved

Read:

Write:

$001A

PARTIDH

Read:

ID15

ID14

ID13

ID12

ID11

ID10

ID9

ID8

Write:

$001B

PARTIDL

Read:

ID7

ID6

ID5

ID4

ID3

ID2

ID1

ID0

Write:

$001C - $001D

MMC map 3 of 4 (Core and Device User Guide, Table 1-4)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$001C

MEMSIZ0

Read: reg_sw0

eep_sw1 eep_sw0

ram_sw2 ram_sw1 ram_sw0

Write:

$001D

MEMSIZ1

Read: rom_sw1 rom_sw0

pag_sw1 pag_sw0

Write:

$001E - $001E

MEBI map 2 of 3 (Core User Guide)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$001E

INTCR

Read:

IRQE

IRQEN

Write:

$001F - $001F

INT map 2 of 2 (Core User Guide)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$001F

HPRIO

Read:

PSEL7

PSEL6

PSEL5

PSEL4

PSEL3

PSEL2

PSEL1

Write:

MC9S12DT128B Device User Guide -- V01.07

$0020 - $0027

Reserved

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$0020 -
$0027

Reserved

Read:

Write:

$0028 - $002F

BKP (Core User Guide)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$0028

BKPCT0

Read:

BKEN

BKFULL

BKBDM

BKTAG

Write:

$0029

BKPCT1

Read:

BK0MBH BK0MBL BK1MBH BK1MBL BK0RWE

BK0RW

BK1RWE

BK1RW

Write:

$002A

BKP0X

Read:

BK0V5

BK0V4

BK0V3

BK0V2

BK0V1

BK0V0

Write:

$002B

BKP0H

Read:

Bit 15

Bit 8

Write:

$002C

BKP0L

Read:

Bit 7

Bit 0

Write:

$002D

BKP1X

Read:

BK1V5

BK1V4

BK1V3

BK1V2

BK1V1

BK1V0

Write:

$002E

BKP1H

Read:

Bit 15

Bit 8

Write:

$002F

BKP1L

Read:

Bit 7

Bit 0

Write:

$0030 - $0031

MMC map 4 of 4 (Core User Guide)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$0030

PPAGE

Read:

PIX5

PIX4

PIX3

PIX2

PIX1

PIX0

Write:

$0031

Reserved

Read:

Write:

$0032 - $0033

MEBI map 3 of 3 (Core User Guide)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$0032

PORTK

Read:

Bit 7

Bit 0

Write:

$0033

DDRK

Read:

Bit 7

Bit 0

Write:

MC9S12DT128B Device User Guide -- V01.07

$0034 - $003F

CRG (Clock and Reset Generator)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$0034

SYNR

Read:

SYN5

SYN4

SYN3

SYN2

SYN1

SYN0

Write:

$0035

REFDV

Read:

REFDV3

REFDV2

REFDV1 REFDV0

Write:

$0036

CTFLG

TEST ONLY

Read:

Write:

$0037

CRGFLG

Read:

RTIF

PORF

LOCKIF

LOCK

TRACK

SCMIF

SCM

Write:

$0038

CRGINT

Read:

RTIE

LOCKIE

SCMIE

Write:

$0039

CLKSEL

Read:

PLLSEL

PSTP

SYSWAI ROAWAI

PLLWAI

CWAI

RTIWAI

COPWAI

Write:

$003A

PLLCTL

Read:

CME

PLLON

AUTO

ACQ

PRE

PCE

SCME

Write:

$003B

RTICTL

Read:

RTR6

RTR5

RTR4

RTR3

RTR2

RTR1

RTR0

Write:

$003C

COPCTL

Read:

WCOP

RSBCK

CR2

CR1

CR0

Write:

$003D

FORBYP

TEST ONLY

Read:

Write:

$003E

CTCTL

TEST ONLY

Read:

Write:

$003F

ARMCOP

Read:

Write:

Bit 7

Bit 0

$0040 - $007F

ECT (Enhanced Capture Timer 16 Bit 8 Channels)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$0040

TIOS

Read:

IOS7

IOS6

IOS5

IOS4

IOS3

IOS2

IOS1

IOS0

Write:

$0041

CFORC

Read:

Write:

FOC7

FOC6

FOC5

FOC4

FOC3

FOC2

FOC1

FOC0

$0042

OC7M

Read:

OC7M7

OC7M6

OC7M5

OC7M4

OC7M3

OC7M2

OC7M1

OC7M0

Write:

$0043

OC7D

Read:

OC7D7

OC7D6

OC7D5

OC7D4

OC7D3

OC7D2

OC7D1

OC7D0

Write:

$0044

TCNT (hi)

Read:

Bit 15

Bit 8

Write:

$0045

TCNT (lo)

Read:

Bit 7

Bit 0

Write:

$0046

TSCR1

Read:

TEN

TSWAI

TSFRZ

TFFCA

Write:

$0047

TTOV

Read:

TOV7

TOV6

TOV5

TOV4

TOV3

TOV2

TOV1

TOV0

Write:

$0048

TCTL1

Read:

OM7

OL7

OM6

OL6

OM5

OL5

OM4

OL4

Write:

$0049

TCTL2

Read:

OM3

OL3

OM2

OL2

OM1

OL1

OM0

OL0

Write:

MC9S12DT128B Device User Guide -- V01.07

$004A

TCTL3

Read:

EDG7B

EDG7A

EDG6B

EDG6A

EDG5B

EDG5A

EDG4B

EDG4A

Write:

$004B

TCTL4

Read:

EDG3B

EDG3A

EDG2B

EDG2A

EDG1B

EDG1A

EDG0B

EDG0A

Write:

$004C

TIE

Read:

C7I

C6I

C5I

C4I

C3I

C2I

C1I

C0I

Write:

$004D

TSCR2

Read:

TOI

TCRE

PR2

PR1

PR0

Write:

$004E

TFLG1

Read:

C7F

C6F

C5F

C4F

C3F

C2F

C1F

C0F

Write:

$004F

TFLG2

Read:

TOF

Write:

$0050

TC0 (hi)

Read:

Bit 15

Bit 8

Write:

$0051

TC0 (lo)

Read:

Bit 7

Bit 0

Write:

$0052

TC1 (hi)

Read:

Bit 15

Bit 8

Write:

$0053

TC1 (lo)

Read:

Bit 7

Bit 0

Write:

$0054

TC2 (hi)

Read:

Bit 15

Bit 8

Write:

$0055

TC2 (lo)

Read:

Bit 7

Bit 0

Write:

$0056

TC3 (hi)

Read:

Bit 15

Bit 8

Write:

$0057

TC3 (lo)

Read:

Bit 7

Bit 0

Write:

$0058

TC4 (hi)

Read:

Bit 15

Bit 8

Write:

$0059

TC4 (lo)

Read:

Bit 7

Bit 0

Write:

$005A

TC5 (hi)

Read:

Bit 15

Bit 8

Write:

$005B

TC5 (lo)

Read:

Bit 7

Bit 0

Write:

$005C

TC6 (hi)

Read:

Bit 15

Bit 8

Write:

$005D

TC6 (lo)

Read:

Bit 7

Bit 0

Write:

$005E

TC7 (hi)

Read:

Bit 15

Bit 8

Write:

$005F

TC7 (lo)

Read:

Bit 7

Bit 0

Write:

$0060

PACTL

Read:

PAEN

PAMOD

PEDGE

CLK1

CLK0

PAOVI

PAI

Write:

$0061

PAFLG

Read:

PAOVF

PAIF

Write:

$0062

PACN3 (hi)

Read:

Bit 7

Bit 0

Write:

$0040 - $007F

ECT (Enhanced Capture Timer 16 Bit 8 Channels)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MC9S12DT128B Device User Guide -- V01.07

$0063

PACN2 (lo)

Read:

Bit 7

Bit 0

Write:

$0064

PACN1 (hi)

Read:

Bit 7

Bit 0

Write:

$0065

PACN0 (lo)

Read:

Bit 7

Bit 0

Write:

$0066

MCCTL

Read:

MCZI

MODMC

RDMCL

MCEN

MCPR1

MCPR0

Write:

ICLAT

FLMC

$0067

MCFLG

Read:

MCZF

POLF3

POLF2

POLF1

POLF0

Write:

$0068

ICPAR

Read:

PA3EN

PA2EN

PA1EN

PA0EN

Write:

$0069

DLYCT

Read:

DLY1

DLY0

Write:

$006A

ICOVW

Read:

NOVW7

NOVW6

NOVW5

NOVW4

NOVW3

NOVW2

NOVW1

NOVW0

Write:

$006B

ICSYS

Read:

SH37

SH26

SH15

SH04

TFMOD

PACMX

BUFEN

LATQ

Write:

$006C

Reserved

Read:

Write:

$006D

TIMTST

Test Only

Read:

TCBYP

Write:

$006E

Reserved

Read:

Write:

$006F

Reserved

Read:

Write:

$0070

PBCTL

Read:

PBEN

PBOVI

Write:

$0071

PBFLG

Read:

PBOVF

Write:

$0072

PA3H

Read:

Bit 7

Bit 0

Write:

$0073

PA2H

Read:

Bit 7

Bit 0

Write:

$0074

PA1H

Read:

Bit 7

Bit 0

Write:

$0075

PA0H

Read:

Bit 7

Bit 0

Write:

$0076

MCCNT (hi)

Read:

Bit 15

Bit 8

Write:

$0077

MCCNT (lo)

Read:

Bit 7

Bit 0

Write:

$0078

TC0H (hi)

Read:

Bit 15

Bit 8

Write:

$0079

TC0H (lo)

Read:

Bit 7

Bit 0

Write:

$007A

TC1H (hi)

Read:

Bit 15

Bit 8

Write:

$007B

TC1H (lo)

Read:

Bit 7

Bit 0

Write:

$0040 - $007F

ECT (Enhanced Capture Timer 16 Bit 8 Channels)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MC9S12DT128B Device User Guide -- V01.07

$007C

TC2H (hi)

Read:

Bit 15

Bit 8

Write:

$007D

TC2H (lo)

Read:

Bit 7

Bit 0

Write:

$007E

TC3H (hi)

Read:

Bit 15

Bit 8

Write:

$007F

TC3H (lo)

Read:

Bit 7

Bit 0

Write:

$0080 - $009F

ATD0 (Analog to Digital Converter 10 Bit 8 Channel)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$0080

ATD0CTL0

Read:

Write:

$0081

ATD0CTL1

Read:

Write:

$0082

ATD0CTL2

Read:

ADPU

AFFC

AWAI

ETRIGLE ETRIGP

ETRIG

ASCIE

ASCIF

Write:

$0083

ATD0CTL3

Read:

S8C

S4C

S2C

S1C

FIFO

FRZ1

FRZ0

Write:

$0084

ATD0CTL4

Read:

SRES8

SMP1

SMP0

PRS4

PRS3

PRS2

PRS1

PRS0

Write:

$0085

ATD0CTL5

Read:

DJM

DSGN

SCAN

MULT

Write:

$0086

ATD0STAT0

Read:

SCF

ETORF

FIFOR

CC2

CC1

CC0

Write:

$0087

Reserved

Read:

Write:

$0088

ATD0TEST0

Read:

Write:

$0089

ATD0TEST1

Read:

Write:

$008A

Reserved

Read:

Write:

$008B

ATD0STAT1

Read:

CCF7

CCF6

CCF5

CCF4

CCF3

CCF2

CCF1

CCF0

Write:

$008C

Reserved

Read:

Write:

$008D

ATD0DIEN

Read:

Bit 7

Bit 0

Write:

$008E

Reserved

Read:

Write:

$008F

PORTAD0

Read:

Bit7

BIT 0

Write:

$0090

ATD0DR0H

Read:

Bit15

Bit8

Write:

$0091

ATD0DR0L

Read:

Bit7

Bit6

Write:

$0040 - $007F

ECT (Enhanced Capture Timer 16 Bit 8 Channels)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MC9S12DT128B Device User Guide -- V01.07

$0092

ATD0DR1H

Read:

Bit15

Bit8

Write:

$0093

ATD0DR1L

Read:

Bit7

Bit6

Write:

$0094

ATD0DR2H

Read:

Bit15

Bit8

Write:

$0095

ATD0DR2L

Read:

Bit7

Bit6

Write:

$0096

ATD0DR3H

Read:

Bit15

Bit8

Write:

$0097

ATD0DR3L

Read:

Bit7

Bit6

Write:

$0098

ATD0DR4H

Read:

Bit15

Bit8

Write:

$0099

ATD0DR4L

Read:

Bit7

Bit6

Write:

$009A

ATD0DR5H

Read:

Bit15

Bit8

Write:

$009B

ATD0DR5L

Read:

Bit7

Bit6

Write:

$009C

ATD0DR6H

Read:

Bit15

Bit8

Write:

$009D

ATD0DR6L

Read:

Bit7

Bit6

Write:

$009E

ATD0DR7H

Read:

Bit15

Bit8

Write:

$009F

ATD0DR7L

Read:

Bit7

Bit6

Write:

$00A0 - $00C7

PWM (Pulse Width Modulator 8 Bit 8 Channel)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$00A0

PWME

Read:

PWME7

PWME6

PWME5

PWME4

PWME3

PWME2

PWME1

PWME0

Write:

$00A1

PWMPOL

Read:

PPOL7

PPOL6

PPOL5

PPOL4

PPOL3

PPOL2

PPOL1

PPOL0

Write:

$00A2

PWMCLK

Read:

PCLK7

PCLK6

PCLK5

PCLK4

PCLK3

PCLK2

PCLK1

PCLK0

Write:

$00A3

PWMPRCLK

Read:

PCKB2

PCKB1

PCKB0

PCKA2

PCKA1

PCKA0

Write:

$00A4

PWMCAE

Read:

CAE7

CAE6

CAE5

CAE4

CAE3

CAE2

CAE1

CAE0

Write:

$00A5

PWMCTL

Read:

CON67

CON45

CON23

CON01

PSWAI

PFRZ

Write:

$00A6

PWMTST

Test Only

Read:

Write:

$00A7

PWMPRSC

Test Only

Read:

Write:

$00A8

PWMSCLA

Read:

Bit 7

Bit 0

Write:

$0080 - $009F

ATD0 (Analog to Digital Converter 10 Bit 8 Channel)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MC9S12DT128B Device User Guide -- V01.07

$00A9

PWMSCLB

Read:

Bit 7

Bit 0

Write:

$00AA

PWMSCNTA

Test Only

Read:

Write:

$00AB

PWMSCNTB

Test Only

Read:

Write:

$00AC

PWMCNT0

Read:

Bit 7

Bit 0

Write:

$00AD

PWMCNT1

Read:

Bit 7

Bit 0

Write:

$00AE

PWMCNT2

Read:

Bit 7

Bit 0

Write:

$00AF

PWMCNT3

Read:

Bit 7

Bit 0

Write:

$00B0

PWMCNT4

Read:

Bit 7

Bit 0

Write:

$00B1

PWMCNT5

Read:

Bit 7

Bit 0

Write:

$00B2

PWMCNT6

Read:

Bit 7

Bit 0

Write:

$00B3

PWMCNT7

Read:

Bit 7

Bit 0

Write:

$00B4

PWMPER0

Read:

Bit 7

Bit 0

Write:

$00B5

PWMPER1

Read:

Bit 7

Bit 0

Write:

$00B6

PWMPER2

Read:

Bit 7

Bit 0

Write:

$00B7

PWMPER3

Read:

Bit 7

Bit 0

Write:

$00B8

PWMPER4

Read:

Bit 7

Bit 0

Write:

$00B9

PWMPER5

Read:

Bit 7

Bit 0

Write:

$00BA

PWMPER6

Read:

Bit 7

Bit 0

Write:

$00BB

PWMPER7

Read:

Bit 7

Bit 0

Write:

$00BC

PWMDTY0

Read:

Bit 7

Bit 0

Write:

$00BD

PWMDTY1

Read:

Bit 7

Bit 0

Write:

$00BE

PWMDTY2

Read:

Bit 7

Bit 0

Write:

$00BF

PWMDTY3

Read:

Bit 7

Bit 0

Write:

$00C0

PWMDTY4

Read:

Bit 7

Bit 0

Write:

$00C1

PWMDTY5

Read:

Bit 7

Bit 0

Write:

$00A0 - $00C7

PWM (Pulse Width Modulator 8 Bit 8 Channel)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MC9S12DT128B Device User Guide -- V01.07

$00C2

PWMDTY6

Read:

Bit 7

Bit 0

Write:

$00C3

PWMDTY7

Read:

Bit 7

Bit 0

Write:

$00C4

PWMSDN

Read:

PWMIF

PWMIE

PWMRSTRT

PWMLVL

PWM7IN

PWM7INL PWM7ENA

Write:

$00C5

Reserved

Read:

Write:

$00C6

Reserved

Read:

Write:

$00C7

Reserved

Read:

Write:

$00C8 - $00CF

SCI0 (Asynchronous Serial Interface)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$00C8

SCI0BDH

Read:

SBR12

SBR11

SBR10

SBR9

SBR8

Write:

$00C9

SCI0BDL

Read:

SBR7

SBR6

SBR5

SBR4

SBR3

SBR2

SBR1

SBR0

Write:

$00CA

SCI0CR1

Read:

LOOPS

SCISWAI

RSRC

WAKE

ILT

Write:

$00CB

SCI0CR2

Read:

TIE

TCIE

RIE

ILIE

RWU

SBK

Write:

$00CC

SCI0SR1

Read:

TDRE

RDRF

IDLE

Write:

$00CD

SCI0SR2

Read:

BRK13

TXDIR

RAF

Write:

$00CE

SCI0DRH

Read:

Write:

$00CF

SCI0DRL

Read:

Write:

$00D0 - $00D7

SCI1 (Asynchronous Serial Interface)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$00D0

SCI1BDH

Read:

SBR12

SBR11

SBR10

SBR9

SBR8

Write:

$00D1

SCI1BDL

Read:

SBR7

SBR6

SBR5

SBR4

SBR3

SBR2

SBR1

SBR0

Write:

$00D2

SCI1CR1

Read:

LOOPS

SCISWAI

RSRC

WAKE

ILT

Write:

$00D3

SCI1CR2

Read:

TIE

TCIE

RIE

ILIE

RWU

SBK

Write:

$00D4

SCI1SR1

Read:

TDRE

RDRF

IDLE

Write:

$00A0 - $00C7

PWM (Pulse Width Modulator 8 Bit 8 Channel)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MC9S12DT128B Device User Guide -- V01.07

$00D5

SCI1SR2

Read:

BRK13

TXDIR

RAF

Write:

$00D6

SCI1DRH

Read:

Write:

$00D7

SCI1DRL

Read:

Write:

$00D8 - $00DF

SPI0 (Serial Peripheral Interface)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$00D8

SPI0CR1

Read:

SPIE

SPE

SPTIE

MSTR

CPOL

CPHA

SSOE

LSBFE

Write:

$00D9

SPI0CR2

Read:

MODFEN BIDIROE

SPISWAI

SPC0

Write:

$00DA

SPI0BR

Read:

SPPR2

SPPR1

SPPR0

SPR2

SPR1

SPR0

Write:

$00DB

SPI0SR

Read:

SPIF

SPTEF

MODF

Write:

$00DC

Reserved

Read:

Write:

$00DD

SPI0DR

Read:

Bit7

Bit0

Write:

$00DE

Reserved

Read:

Write:

$00DF

Reserved

Read:

Write:

$00E0 - $00E7

IIC (Inter IC Bus)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$00E0

IBAD

Read:

ADR7

ADR6

ADR5

ADR4

ADR3

ADR2

ADR1

Write:

$00E1

IBFD

Read:

IBC7

IBC6

IBC5

IBC4

IBC3

IBC2

IBC1

IBC0

Write:

$00E2

IBCR

Read:

IBEN

IBIE

MS/SL

TX/RX

TXAK

IBSWAI

Write:

RSTA

$00E3

IBSR

Read:

TCF

IAAS

IBB

IBAL

SRW

IBIF

RXAK

Write:

$00E4

IBDR

Read:

D 0

Write:

$00E5

Reserved

Read:

Write:

$00E6

Reserved

Read:

Write:

$00E7

Reserved

Read:

Write:

$00D0 - $00D7

SCI1 (Asynchronous Serial Interface)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MC9S12DT128B Device User Guide -- V01.07

$00E8 - $00EF

BDLC (Byte Level Data Link Controller J1850)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$00E8

DLCBCR1

Read:

IMSG

CLKS

WCM

Write:

$00E9

DLCBSVR

Read:

Write:

$00EA

DLCBCR2

Read:

SMRST

DLOOP

RX4XE

NBFS

TEOD

TSIFR

TMIFR1

TMIFR0

Write:

$00EB

DLCBDR

Read:

Write:

$00EC

DLCBARD

Read:

RXPOL

BO3

BO2

BO1

BO0

Write:

$00ED

DLCBRSR

Read:

Write:

$00EE

DLCSCR

Read:

BDLCE

Write:

$00EF

DLCBSTAT

Read:

IDLE

Write:

$00F0 - $00F7

SPI1 (Serial Peripheral Interface)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$00F0

SPI1CR1

Read:

SPIE

SPE

SPTIE

MSTR

CPOL

CPHA

SSOE

LSBFE

Write:

$00F1

SPI1CR2

Read:

MODFEN BIDIROE

SPISWAI

SPC0

Write:

$00F2

SPI1BR

Read:

SPPR2

SPPR1

SPPR0

SPR2

SPR1

SPR0

Write:

$00F3

SPI1SR

Read:

SPIF

SPTEF

MODF

Write:

$00F4

Reserved

Read:

Write:

$00F5

SPI1DR

Read:

Bit7

Bit0

Write:

$00F6

Reserved

Read:

Write:

$00F7

Reserved

Read:

Write:

$00F8 - $00FF

Reserved

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$00F8 -
$00FF

Reserved

Read:

Write:

MC9S12DT128B Device User Guide -- V01.07

$0100 - $010F

Flash Control Register (fts128k2)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$0100

FCLKDIV

Read: FDIVLD

PRDIV8

FDIV5

FDIV4

FDIV3

FDIV2

FDIV1

FDIV0

Write:

$0101

FSEC

Read:

KEYEN

NV6

NV5

NV4

NV3

NV2

SEC1

SEC0

Write:

$0102

FTSTMOD

Read:

WRALL

Write:

$0103

FCNFG

Read:

CBEIE

CCIE

KEYACC

BKSEL1

BKSEL0

Write:

$0104

FPROT

Read:

FPOPEN

NV6

FPHDIS

FPHS1

FPHS0

FPLDIS

FPLS1

FPLS0

Write:

$0105

FSTAT

Read:

CBEIF

CCIF

PVIOL

ACCERR

BLANK

Write:

$0106

FCMD

Read:

CMDB6

CMDB5

CMDB2

CMDB0

Write:

$0107

Reserved for

Factory Test

Read:

Write:

$0108

FADDRHI

Read:

Bit 14

Bit 8

Write:

$0109

FADDRLO

Read:

Bit 7

Bit 0

Write:

$010A

FDATAHI

Read:

Bit 15

Bit 8

Write:

$010B

FDATALO

Read:

Bit 7

Bit 0

Write:

$010C -
$010F

Reserved

Read:

Write:

$0110 - $011B

EEPROM Control Register (eets2k)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$0110

ECLKDIV

Read: EDIVLD

PRDIV8

EDIV5

EDIV4

EDIV3

EDIV2

EDIV1

EDIV0

Write:

$0111

Reserved

Read:

Write:

$0112

Reserved for

Factory Test

Read:

Write:

$0113

ECNFG

Read:

CBEIE

CCIE

Write:

$0114

EPROT

Read:

EPOPEN

NV6

NV5

NV4

EPDIS

EP2

EP1

EP0

Write:

$0115

ESTAT

Read:

CBEIF

CCIF

PVIOL

ACCERR

BLANK

Write:

$0116

ECMD

Read:

CMDB6

CMDB5

CMDB2

CMDB0

Write:

$0117

Reserved for

Factory Test

Read:

Write:

$0108

EADDRHI

Read:

Bit 9

Bit 8

Write:

MC9S12DT128B Device User Guide -- V01.07

$0109

EADDRLO

Read:

Bit 7

Bit 0

Write:

$010A

EDATAHI

Read:

Bit 15

Bit 8

Write:

$010B

EDATALO

Read:

Bit 7

Bit 0

Write:

$011C - $011F

Reserved for RAM Control Register

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$011C -
$011F

Reserved

Read:

Write:

$0120 - $013F

ATD1 (Analog to Digital Converter 10 Bit 8 Channel)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$0120

ATD1CTL0

Read:

Write:

$0121

ATD1CTL1

Read:

Write:

$0122

ATD1CTL2

Read:

ADPU

AFFC

AWAI

ETRIGLE ETRIGP

ETRIG

ASCIE

ASCIF

Write:

$0123

ATD1CTL3

Read:

S8C

S4C

S2C

S1C

FIFO

FRZ1

FRZ0

Write:

$0124

ATD1CTL4

Read:

SRES8

SMP1

SMP0

PRS4

PRS3

PRS2

PRS1

PRS0

Write:

$0125

ATD1CTL5

Read:

DJM

DSGN

SCAN

MULT

Write:

$0126

ATD1STAT0

Read:

SCF

ETORF

FIFOR

CC2

CC1

CC0

Write:

$0127

Reserved

Read:

Write:

$0128

ATD1TEST0

Read:

Write:

$0129

ATD1TEST1

Read:

Write:

$012A

Reserved

Read:

Write:

$012B

ATD1STAT1

Read:

CCF7

CCF6

CCF5

CCF4

CCF3

CCF2

CCF1

CCF0

Write:

$012C

Reserved

Read:

Write:

$012D

ATD1DIEN

Read:

Bit 7

Bit 0

Write:

$012E

Reserved

Read:

Write:

$012F

PORTAD1

Read:

Bit7

BIT 0

Write:

$0110 - $011B

EEPROM Control Register (eets2k)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MC9S12DT128B Device User Guide -- V01.07

$0130

ATD1DR0H

Read:

Bit15

Bit8

Write:

$0131

ATD1DR0L

Read:

Bit7

Bit6

Write:

$0132

ATD1DR1H

Read:

Bit15

Bit8

Write:

$0133

ATD1DR1L

Read:

Bit7

Bit6

Write:

$0134

ATD1DR2H

Read:

Bit15

Bit8

Write:

$0135

ATD1DR2L

Read:

Bit7

Bit6

Write:

$0136

ATD1DR3H

Read:

Bit15

Bit8

Write:

$0137

ATD1DR3L

Read:

Bit7

Bit6

Write:

$0138

ATD1DR4H

Read:

Bit15

Bit8

Write:

$0139

ATD1DR4L

Read:

Bit7

Bit6

Write:

$013A

ATD1DR5H

Read:

Bit15

Bit8

Write:

$013B

ATD1DR5L

Read:

Bit7

Bit6

Write:

$013C

ATD1DR6H

Read:

Bit15

Bit8

Write:

$013D

ATD1DR6L

Read:

Bit7

Bit6

Write:

$013E

ATD1DR7H

Read:

Bit15

Bit8

Write:

$013F

ATD1DR7L

Read:

Bit7

Bit6

Write:

$0140 - $017F

CAN0 (Motorola Scalable CAN - MSCAN)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$0140

CAN0CTL0

Read:

RXFRM

RXACT

CSWAI

SYNCH

TIME

WUPE

SLPRQ

INITRQ

Write:

$0141

CAN0CTL1

Read:

CANE

CLKSRC

LOOPB

LISTEN

WUPM

SLPAK

INITAK

Write:

$0142

CAN0BTR0

Read:

SJW1

SJW0

BRP5

BRP4

BRP3

BRP2

BRP1

BRP0

Write:

$0143

CAN0BTR1

Read:

SAMP

TSEG22

TSEG21

TSEG20

TSEG13

TSEG12

TSEG11

TSEG10

Write:

$0144

CAN0RFLG

Read:

WUPIF

CSCIF

RSTAT1

RSTAT0

TSTAT1

TSTAT0

OVRIF

RXF

Write:

$0145

CAN0RIER

Read:

WUPIE

CSCIE

RSTATE1 RSTATE0 TSTATE1 TSTATE0

OVRIE

RXFIE

Write:

$0120 - $013F

ATD1 (Analog to Digital Converter 10 Bit 8 Channel)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MC9S12DT128B Device User Guide -- V01.07

$0146

CAN0TFLG

Read:

TXE2

TXE1

TXE0

Write:

$0147

CAN0TIER

Read:

TXEIE2

TXEIE1

TXEIE0

Write:

$0148

CAN0TARQ

Read:

ABTRQ2 ABTRQ1 ABTRQ0

Write:

$0149

CAN0TAAK

Read:

ABTAK2

ABTAK1

ABTAK0

Write:

$014A

CAN0TBSEL

Read:

TX2

TX1

TX0

Write:

$014B

CAN0IDAC

Read:

IDAM1

IDAM0

IDHIT2

IDHIT1

IDHIT0

Write:

$014C

Reserved

Read:

Write:

$014D

Reserved

Read:

Write:

$014E

CAN0RXERR

Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0

Write:

$014F

CAN0TXERR

Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0

Write:

$0150 -
$0153

CAN0IDAR0 -

CAN0IDAR3

Read:

AC7

AC6

AC5

AC4

AC3

AC2

AC1

AC0

Write:

$0154 -
$0157

CAN0IDMR0 -

CAN0IDMR3

Read:

AM7

AM6

AM5

AM4

AM3

AM2

AM1

AM0

Write:

$0158 -
$015B

CAN0IDAR4 -

CAN0IDAR7

Read:

AC7

AC6

AC5

AC4

AC3

AC2

AC1

AC0

Write:

$015C -
$015F

CAN0IDMR4 -

CAN0IDMR7

Read:

AM7

AM6

AM5

AM4

AM3

AM2

AM1

AM0

Write:

$0160 -
$016F

CAN0RXFG

Read:

FOREGROUND RECEIVE BUFFER see Table 1-2

Write:

$0170 -
$017F

CAN0TXFG

Read:

FOREGROUND TRANSMIT BUFFER see Table 1-2

Write:

Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$xxx0

Extended ID

Read:

ID28

ID27

ID26

ID25

ID24

ID23

ID22

ID21

Standard ID

Read:

ID10

ID9

ID8

ID7

ID6

ID5

ID4

ID3

CANxRIDR0

Write:

$xxx1

Extended ID

Read:

ID20

ID19

ID18

SRR=1

IDE=1

ID17

ID16

ID15

Standard ID

Read:

ID2

ID1

ID0

RTR

IDE=0

CANxRIDR1

Write:

$xxx2

Extended ID

Read:

ID14

ID13

ID12

ID11

ID10

ID9

ID8

ID7

Standard ID

Read:

CANxRIDR2

Write:

$xxx3

Extended ID

Read:

ID6

ID5

ID4

ID3

ID2

ID1

ID0

RTR

Standard ID

Read:

CANxRIDR3

Write:

$xxx4-
$xxxB

CANxRDSR0 -

CANxRDSR7

Read:

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Write:

$0140 - $017F

CAN0 (Motorola Scalable CAN - MSCAN)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MC9S12DT128B Device User Guide -- V01.07

$xxxC

CANRxDLR

Read:

DLC3

DLC2

DLC1

DLC0

Write:

$xxxD

Reserved

Read:

Write:

$xxxE

CANxRTSRH

Read:

TSR15

TSR14

TSR13

TSR12

TSR11

TSR10

TSR9

TSR8

Write:

$xxxF

CANxRTSRL

Read:

TSR7

TSR6

TSR5

TSR4

TSR3

TSR2

TSR1

TSR0

Write:

$xx10

Extended ID

Read:

ID28

ID27

ID26

ID25

ID24

ID23

ID22

ID21

CANxTIDR0

Write:

Standard ID

Read:

ID10

ID9

ID8

ID7

ID6

ID5

ID4

ID3

Write:

$xx11

Extended ID

Read:

ID20

ID19

ID18

SRR=1

IDE=1

ID17

ID16

ID15

CANxTIDR1

Write:

Standard ID

Read:

ID2

ID1

ID0

RTR

IDE=0

Write:

$xx12

Extended ID

Read:

ID14

ID13

ID12

ID11

ID10

ID9

ID8

ID7

CANxTIDR2

Write:

Standard ID

Read:

Write:

$xx13

Extended ID

Read:

ID6

ID5

ID4

ID3

ID2

ID1

ID0

RTR

CANxTIDR3

Write:

Standard ID

Read:

Write:

$xx14-
$xx1B

CANxTDSR0 -

CANxTDSR7

Read:

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Write:

$xx1C

CANxTDLR

Read:

DLC3

DLC2

DLC1

DLC0

Write:

$xx1D

CONxTTBPR

Read:

PRIO7

PRIO6

PRIO5

PRIO4

PRIO3

PRIO2

PRIO1

PRIO0

Write:

$xx1E

CANxTTSRH

Read:

TSR15

TSR14

TSR13

TSR12

TSR11

TSR10

TSR9

TSR8

Write:

$xx1F

CANxTTSRL

Read:

TSR7

TSR6

TSR5

TSR4

TSR3

TSR2

TSR1

TSR0

Write:

$0180 - $01BF

CAN1 (Motorola Scalable CAN - MSCAN)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$0180

CAN1CTL0

Read:

RXFRM

RXACT

CSWAI

SYNCH

TIME

WUPE

SLPRQ

INITRQ

Write:

$0181

CAN1CTL1

Read:

CANE

CLKSRC

LOOPB

LISTEN

WUPM

SLPAK

INITAK

Write:

$0182

CAN1BTR0

Read:

SJW1

SJW0

BRP5

BRP4

BRP3

BRP2

BRP1

BRP0

Write:

$0183

CAN1BTR1

Read:

SAMP

TSEG22

TSEG21

TSEG20

TSEG13

TSEG12

TSEG11

TSEG10

Write:

$0184

CAN1RFLG

Read:

WUPIF

CSCIF

RSTAT1

RSTAT0

TSTAT1

TSTAT0

OVRIF

RXF

Write:

Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MC9S12DT128B Device User Guide -- V01.07

$0185

CAN1RIER

Read:

WUPIE

CSCIE

RSTATE1 RSTATE0 TSTATE1 TSTATE0

OVRIE

RXFIE

Write:

$0186

CAN1TFLG

Read:

TXE2

TXE1

TXE0

Write:

$0187

CAN1TIER

Read:

TXEIE2

TXEIE1

TXEIE0

Write:

$0188

CAN1TARQ

Read:

ABTRQ2 ABTRQ1 ABTRQ0

Write:

$0189

CAN1TAAK

Read:

ABTAK2

ABTAK1

ABTAK0

Write:

$018A

CAN1TBSEL

Read:

TX2

TX1

TX0

Write:

$018B

CAN1IDAC

Read:

IDAM1

IDAM0

IDHIT2

IDHIT1

IDHIT0

Write:

$018C

Reserved

Read:

Write:

$018D

Reserved

Read:

Write:

$0184E

CAN1RXERR

Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0

Write:

$018F

CAN1TXERR

Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0

Write:

$0190 -
$0193

CAN1IDAR0 -

CAN1IDAR3

Read:

AC7

AC6

AC5

AC4

AC3

AC2

AC1

AC0

Write:

$0194 -
$0197

CAN1IDMR0 -

CAN1IDMR3

Read:

AM7

AM6

AM5

AM4

AM3

AM2

AM1

AM0

Write:

$0198 -
$019B

CAN1IDAR4 -

CAN1IDAR7

Read:

AC7

AC6

AC5

AC4

AC3

AC2

AC1

AC0

Write:

$019C -
$019F

CAN1IDMR4 -

CAN1IDMR7

Read:

AM7

AM6

AM5

AM4

AM3

AM2

AM1

AM0

Write:

$0160 -
$016F

CAN0RXFG

Read:

FOREGROUND RECEIVE BUFFER see Table 1-2

Write:

$0170 -
$017F

CAN0TXFG

Read:

FOREGROUND TRANSMIT BUFFER see Table 1-2

Write:

$01C0 - $01FF

Reserved

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$01C0 -
$01FF

Reserved

Read:

Write:

$0200 - $023F

Reserved

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$020C -
$023F

Reserved

Read:

Write:

$0180 - $01BF

CAN1 (Motorola Scalable CAN - MSCAN)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MC9S12DT128B Device User Guide -- V01.07

$0240 - $027F

PIM (Port Integration Module)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$0240

PTT

Read:

PTT7

PTT6

PTT5

PTT4

PTT3

PTT2

PTT1

PTT0

Write:

$0241

PTIT

Read:

PTIT7

PTIT6

PTIT5

PTIT4

PTIT3

PTIT2

PTIT1

PTIT0

Write:

$0242

DDRT

Read:

DDRT7

DDRT5

DDRT4

DDRT3

DDRT2

DDRT1

DDRT0

Write:

$0243

RDRT

Read:

RDRT7

RDRT6

RDRT5

RDRT4

RDRT3

RDRT2

RDRT1

RDRT0

Write:

$0244

PERT

Read:

PERT7

PERT6

PERT5

PERT4

PERT3

PERT2

PERT1

PERT0

Write:

$0245

PPST

Read:

PPST7

PPST6

PPST5

PPST4

PPST3

PPST2

PPST1

PPST0

Write:

$0246

Reserved

Read:

Write:

$0247

Reserved

Read:

Write:

$0248

PTS

Read:

PTS7

PTS6

PTS5

PTS4

PTS3

PTS2

PTS1

PTS0

Write:

$0249

PTIS

Read:

PTIS7

PTIS6

PTIS5

PTIS4

PTIS3

PTIS2

PTIS1

PTIS0

Write:

$024A

DDRS

Read:

DDRS7

DDRS5

DDRS4

DDRS3

DDRS2

DDRS1

DDRS0

Write:

$024B

RDRS

Read:

RDRS7

RDRS6

RDRS5

RDRS4

RDRS3

RDRS2

RDRS1

RDRS0

Write:

$024C

PERS

Read:

PERS7

PERS6

PERS5

PERS4

PERS3

PERS2

PERS1

PERS0

Write:

$024D

PPSS

Read:

PPSS7

PPSS6

PPSS5

PPSS4

PPSS3

PPSS2

PPSS1

PPSS0

Write:

$024E

WOMS

Read:

WOMS7

WOMS6

WOMS5

WOMS4

WOMS3

WOMS2

WOMS1

WOMS0

Write:

$024F

Reserved

Read:

Write:

$0250

PTM

Read:

PTM7

PTM6

PTM5

PTM4

PTM3

PTM2

PTM1

PTM0

Write:

$0251

PTIM

Read:

PTIM7

PTIM6

PTIM5

PTIM4

PTIM3

PTIM2

PTIM1

PTIM0

Write:

$0252

DDRM

Read:

DDRM7

DDRM5

DDRM4

DDRM3

DDRM2

DDRM1

DDRM0

Write:

$0253

RDRM

Read:

RDRM7

RDRM6

RDRM5

RDRM4

RDRM3

RDRM2

RDRM1

RDRM0

Write:

$0254

PERM

Read:

PERM7

PERM6

PERM5

PERM4

PERM3

PERM2

PERM1

PERM0

Write:

$0255

PPSM

Read:

PPSM7

PPSM6

PPSM5

PPSM4

PPSM3

PPSM2

PPSM1

PPSM0

Write:

$0256

WOMM

Read:

WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0

Write:

$0257

MODRR

Read:

MODRR5 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0

Write:

$0258

PTP

Read:

PTP7

PTP6

PTP5

PTP4

PTP3

PTP2

PTP1

PTP0

Write:

MC9S12DT128B Device User Guide -- V01.07

$0259

PTIP

Read:

PTIP7

PTIP6

PTIP5

PTIP4

PTIP3

PTIP2

PTIP1

PTIP0

Write:

$025A

DDRP

Read:

DDRP7

DDRP5

DDRP4

DDRP3

DDRP2

DDRP1

DDRP0

Write:

$025B

RDRP

Read:

RDRP7

RDRP6

RDRP5

RDRP4

RDRP3

RDRP2

RDRP1

RDRP0

Write:

$025C

PERP

Read:

PERP7

PERP6

PERP5

PERP4

PERP3

PERP2

PERP1

PERP0

Write:

$025D

PPSP

Read:

PPSP7

PPSP6

PPSP5

PPSP4

PPSP3

PPSP2

PPSP1

PPSS0

Write:

$025E

PIEP

Read:

PIEP7

PIEP6

PIEP5

PIEP4

PIEP3

PIEP2

PIEP1

PIEP0

Write:

$025F

PIFP

Read:

PIFP7

PIFP6

PIFP5

PIFP4

PIFP3

PIFP2

PIFP1

PIFP0

Write:

$0260

PTH

Read:

PTH7

PTH6

PTH5

PTH4

PTH3

PTH2

PTH1

PTH0

Write:

$0261

PTIH

Read:

PTIH7

PTIH6

PTIH5

PTIH4

PTIH3

PTIH2

PTIH1

PTIH0

Write:

$0262

DDRH

Read:

DDRH7

DDRH5

DDRH4

DDRH3

DDRH2

DDRH1

DDRH0

Write:

$0263

RDRH

Read:

RDRH7

RDRH6

RDRH5

RDRH4

RDRH3

RDRH2

RDRH1

RDRH0

Write:

$0264

PERH

Read:

PERH7

PERH6

PERH5

PERH4

PERH3

PERH2

PERH1

PERH0

Write:

$0265

PPSH

Read:

PPSH7

PPSH6

PPSH5

PPSH4

PPSH3

PPSH2

PPSH1

PPSH0

Write:

$0266

PIEH

Read:

PIEH7

PIEH6

PIEH5

PIEH4

PIEH3

PIEH2

PIEH1

PIEH0

Write:

$0267

PIFH

Read:

PIFH7

PIFH6

PIFH5

PIFH4

PIFH3

PIFH2

PIFH1

PIFH0

Write:

$0268

PTJ

Read:

PTJ7

PTJ6

PTJ1

PTJ0

Write:

$0269

PTIJ

Read:

PTIJ7

PTIJ6

PTIJ1

PTIJ0

Write:

$026A

DDRJ

Read:

DDRJ7

DDRJ1

DDRJ0

Write:

$026B

RDRJ

Read:

RDRJ7

RDRJ6

RDRJ1

RDRJ0

Write:

$026C

PERJ

Read:

PERJ7

PERJ6

PERJ1

PERJ0

Write:

$026D

PPSJ

Read:

PPSJ7

PPSJ6

PPSJ1

PPSJ0

Write:

$026E

PIEJ

Read:

PIEJ7

PIEJ6

PIEJ1

PIEJ0

Write:

$026F

PIFJ

Read:

PIFJ7

PIFJ6

PIFJ1

PIFJ0

Write:

$0270 -
$027F

Reserved

Read:

Write:

$0240 - $027F

PIM (Port Integration Module)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MC9S12DT128B Device User Guide -- V01.07

$0280 - $02BF

CAN4 (Motorola Scalable CAN - MSCAN)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$0280

CAN4CTL0

Read:

RXFRM

RXACT

CSWAI

SYNCH

TIME

WUPE

SLPRQ

INITRQ

Write:

$0281

CAN4CTL1

Read:

CANE

CLKSRC

LOOPB

LISTEN

WUPM

SLPAK

INITAK

Write:

$0282

CAN4BTR0

Read:

SJW1

SJW0

BRP5

BRP4

BRP3

BRP2

BRP1

BRP0

Write:

$0283

CAN4BTR1

Read:

SAMP

TSEG22

TSEG21

TSEG20

TSEG13

TSEG12

TSEG11

TSEG10

Write:

$0284

CAN4RFLG

Read:

WUPIF

CSCIF

RSTAT1

RSTAT0

TSTAT1

TSTAT0

OVRIF

RXF

Write:

$0285

CAN4RIER

Read:

WUPIE

CSCIE

RSTATE1 RSTATE0 TSTATE1 TSTATE0

OVRIE

RXFIE

Write:

$0286

CAN4TFLG

Read:

TXE2

TXE1

TXE0

Write:

$0287

CAN4TIER

Read:

TXEIE2

TXEIE1

TXEIE0

Write:

$0288

CAN4TARQ

Read:

ABTRQ2 ABTRQ1 ABTRQ0

Write:

$0289

CAN4TAAK

Read:

ABTAK2

ABTAK1

ABTAK0

Write:

$028A

CAN4TBSEL

Read:

TX2

TX1

TX0

Write:

$028B

CAN4IDAC

Read:

IDAM1

IDAM0

IDHIT2

IDHIT1

IDHIT0

Write:

$028C

Reserved

Read:

Write:

$028D

Reserved

Read:

Write:

$028E

CAN4RXERR

Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0

Write:

$028F

CAN4TXERR

Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0

Write:

$0290 -
$0293

CAN0IDAR0 -

CAN0IDAR3

Read:

AC7

AC6

AC5

AC4

AC3

AC2

AC1

AC0

Write:

$0294 -
$0297

CAN0IDMR0 -

CAN0IDMR3

Read:

AM7

AM6

AM5

AM4

AM3

AM2

AM1

AM0

Write:

$0298 -
$029B

CAN0IDAR4 -

CAN0IDAR7

Read:

AC7

AC6

AC5

AC4

AC3

AC2

AC1

AC0

Write:

$029C -
$029F

CAN0IDMR4 -

CAN0IDMR7

Read:

AM7

AM6

AM5

AM4

AM3

AM2

AM1

AM0

$02A0 -
$02AF

CAN4RXFG

Read:

FOREGROUND RECEIVE BUFFER see Table 1-2

Write:

$02B0 -
$02BF

CAN4TXFG

Read:

FOREGROUND TRANSMIT BUFFER see Table 1-2

Write:

MC9S12DT128B Device User Guide -- V01.07

$02C0 - $02FF

Reserved

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$02C0 -
$02FF

Reserved

Read:

Write:

$0300 - $035F

Byteflight

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$0300

BFMCR

Read:

INITRQ

MASTER

ALARM

SLPAK

SLPRQ

WPULSE

SSWAI

INITAK

Write:

$0301

BFFSIZR

Read:

FSIZ4

FSIZ3

FSIZ2

FSIZ1

FSIZ0

Write:

$0302

BFTCR1

Read:

TWX0T7 TWX0T6 TWX0T5 TWX0T4 TWX0T3 TWX0T2 TWX0T1 TWX0T0

Write:

$0303

BFTCR2

Read:

TWX0R7 TWX0R6 TWX0R5 TWX0R4 TWX0R3 TWX0R2 TWX0R1 TWX0R0

Write:

$0304

BFTCR3

Read:

TWX0D7 TWX0D6 TWX0D5 TWX0D4 TWX0D3 TWX0D2 TWX0D1 TWX0D0

Write:

$0305

BFIDX

Read: GETIDX3 GETIDX2 GETIDX1 GETIDX0 PUTIDX3 PUTIDX2 PUTIDX1 PUTIDX0

Write:

$0306

BFRISR

Read: RCVFIF

RXIF

SYNAIF

SYNNIF

SLMMIF

XSYNIF

OPTDF

Write:

$0307

BFGISR

Read:

TXIF

OVRNIF

ERRIF

SYNEIF

SYNLIF

ILLPIF

LOCKIF

WAKEIF

Write:

$0308

BFRIER

Read:

RCVFIE

RXIE

SYNAIE

SYNNIE

SLMMIE

XSYNIE

Write:

$0309

BFGIER

Read:

TXIE

OVRNIE

ERRIE

SYNEIE

SYNLIE

ILLPIE

LOCKIE

WAKEIE

Write:

$030A

BFRIVEC

Read:

RIVEC3

RIVEC2

RIVEC1

RIVEC0

Write:

$030B

BFTIVEC

Read:

TIVEC3

TIVEC2

TIVEC1

TIVEC0

Write:

$030C

BFFIDAC

Read:

FIDAC7

FIDAC6

FIDAC5

FIDAC4

FIDAC3

FIDAC2

FIDAC1

FIDAC0

Write:

$030D

BFFIDMR

Read:

FIDMR7

FIDMR6

FIDMR5

FIDMR4

FIDMR3

FIDMR2

FIDMR1

FIDMR0

Write:

$030E

BFMVR

Read:

MVR7

MVR6

MVR5

MVR4

MVR3

MVR2

MVR1

MVR0

Write:

$030F

Reserved

Read:

Write:

$0310

BFPCTLBF

Read:

PMEREN

PSLMEN PERREN PROKEN PSYNEN

BFEN

Write:

$0311

Reserved

Read:

Write:

$0312

BFBUFLOCK

Read:

TXBUFL

OCK

RXBUFL

OCK

Write:

$0313

Reserved

for Test

Read:

Write:

$0314

BFFIDRJ

Read:

FIDRJ7

FIDRJ6

FIDRJ5

FIDRJ4

FIDRJ3

FIDRJ2

FIDRJ1

FIDRJ0

Write:

MC9S12DT128B Device User Guide -- V01.07

$0315

Reserved

for Test

Read:

Write:

$0316

Reserved

for Test

Read:

Write:

$0317

Reserved

for Test

Read:

Write:

$0318

Reserved

for Test

Read:

Write:

$0319

Reserved

for Test

Read:

Write:

$031A

Reserved

for Test

Read:

Write:

$031B

Reserved

for Test

Read:

Write:

$031C

Reserved

for Test

Read:

Write:

$031D

Reserved

for Test

Read:

Write:

$031E

Reserved

for Test

Read:

Write:

$031F

Reserved

for Test

Read:

Write:

$0320

BFTIDENT

Read:

Bit 7

Bit 0

Write:

$0321

BFTLEN

Read:

Bit 7

Bit 0

Write:

$0322 -
$032D

BFTDATA0-

BFTDATA11

Read:

Bit 7

Bit 0

Write:

$032E -
$032F

Unimplemente

Read:

Bit 7

Bit 0

Write:

$0330

BFRIDENT

Read:

Bit 7

Bit 0

Write:

$0331

BFRLEN

Read:

Bit 7

Bit 0

Write:

$0332 -
$033D

BFRDATA0-

BFRDATA11

Read:

Bit 7

Bit 0

Write:

$033E-
$033F

Unimplemente

Read:

Bit 7

Bit 0

Write:

$0340

BFFIDENT

Read:

Bit 7

Bit 0

Write:

$0341

BFFLEN

Read:

Bit 7

Bit 0

Write:

$0342 -
$034D

BFFDATA0-

BFFDATA11

Read:

Bit 7

Bit 0

Write:

$034E -
$034F

Unimplemente

Read:

Bit 7

Bit 0

Write:

$0350 -
$035F

BFBUFCTL0 -
BFBUFCTL15

Read:

IFLG

IENA

LOCK

ABTAK

ABTRQ

CFG

Write:

$0300 - $035F

Byteflight

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MC9S12DT128B Device User Guide -- V01.07

1.6 Part ID Assignments

The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after
reset). The read-only value is a unique part ID for each revision of the chip.

Table 1-3

shows the assigned

part ID number.

The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C
and $001D after reset).

Table 1-4

shows the read-only values of these registers. Refer to section Module

Mapping and Control (MMC) of HCS12 Core User Guide for further details.

$0360 - $03FF

Reserved

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$0360 -
$03FF

Reserved

Read:

Write:

Table 1-3 Assigned Part ID Numbers

Device

Mask Set Number

Part ID

NOTES

1. The coding is as follows:
Bit 15-12: Major family identifier
Bit 11-8: Minor family identifier
Bit 7-4: Major mask set revision number including FAB transfers
Bit 3-0: Minor - non full - mask set revision

MC9S12DT128B

0L85D

$0100

MC9S12DT128B

1L85D

$0101

Table 1-4 Memory size registers

Register name

Value

MEMSIZ0

$13

MEMSIZ1

$80

MC9S12DT128B Device User Guide -- V01.07

Figure 2-1 Pin assignments 112 LQFP for MC9S12DT128B,MC9S12DG128B,

MC9S12DJ128B, MC9S12DB128B

VRH
VDDA
PAD15/AN15/ETRIG1
PAD07/AN07/ETRIG0
PAD14/AN14
PAD06/AN06
PAD13/AN13
PAD05/AN05
PAD12/AN12
PAD04/AN04
PAD11/AN11
PAD03/AN03
PAD10/AN10
PAD02/AN02
PAD09/AN09
PAD01/AN01
PAD08/AN08
PAD00/AN00
VSS2
VDD2
PA7/ADDR15/DATA15
PA6/ADDR14/DATA14
PA5/ADDR13/DATA13
PA4/ADDR12/DATA12
PA3/ADDR11/DATA11
PA2/ADDR10/DATA10
PA1/ADDR9/DATA9
PA0/ADDR8/DATA8

PP4/KWP4/PWM4

PP5/KPW5/PWM5

PP6/KWP6/PWM6

PP7/KWP7/PWM7

PK7/

ECS/R

OMCTL

VDDX

VSSX

PM0/RXCAN0/RXB

PM1/TXCAN0/TXB

PM2/RX_BF/RXCAN1/RXCAN0/MISO0

PM3/TX_BF/TXCAN1/TXCAN0/

SS0

PM4/BF_PSYN/RXCAN0/RXCAN4/MOSI0

PM5/BF_PR

OK/TXCAN0/TXCAN4/SCK0

PJ6/KWJ6/RXCAN4/SD

PJ7/KWJ7/TXCAN4/SCL

VREGEN

PS7/

SS0

PS6/SCK0

PS5/MOSI0

PS4/MISO0

PS3/TXD1

PS2/RXD1

PS1/TXD0

PS0/RXD0

PM6/BF_PERR/RXCAN4

PM7/BF_PSLM/TXCAN4

VSSA

VRL

SS1/PWM3/KWP3/PP3

SCK1/PWM2/KWP2/PP2

MOSI1/PWM1/KWP1/PP1
MISO1/PWM0/KWP0/PP0

XADDR17/PK3
XADDR16/PK2
XADDR15/PK1
XADDR14/PK0

IOC0/PT0
IOC1/PT1
IOC2/PT2
IOC3/PT3

VDD1

VSS1

IOC4/PT4
IOC5/PT5
IOC6/PT6
IOC7/PT7

XADDR19/PK5
XADDR18/PK4

KWJ1/PJ1
KWJ0/PJ0

MODC/TAGHI/BKGD

ADDR0/DATA0/PB0
ADDR1/DATA1/PB1
ADDR2/DATA2/PB2
ADDR3/DATA3/PB3
ADDR4/DATA4/PB4

ADDR5/D

A
T
A5/PB5

ADDR6/D

A
T
A6/PB6

ADDR7/D

A
T
A7/PB7

KWH7/PH7

KWH6/PH6

KWH5/PH5

KWH4/PH4

XCLKS/NO

CC/PE7

MODB/IPIPE1/PE6

MOD

A/IPIPE0/PE5

ECLK/PE4

VSSR

VDDR

RESET

VDDPLL

XFC

VSSPLL

EXT

TEST

SS1/KWH3/PH3

SCK1/KWH2/PH2

MOSI1/KWH1/PH1

MISO1/KWH0/PH0

LSTRB/

T
A

GLO/PE3

W/PE2

IRQ/PE1

XIRQ/PE0

Signals shown in Bold are not available on the 80 Pin Package

MC9S12DT128B, MC9S12DG128B,

MC9S12DJ128B, MC9S12DB128B

112LQFP

112

111

110

109

108

107

106

105

104

103

102

101

100

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57

MC9S12DT128B Device User Guide -- V01.07

Figure 2-2 Pin Assignments in 80 QFP for MC9S12DG128B, MC9S12DJ128B Bondout

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

MC9S12DG128B, MC9S12DJ128B

80 QFP

VRH
VDDA
PAD07/AN07/ETRIG0
PAD06/AN06
PAD05/AN05
PAD04/AN04
PAD03/AN03
PAD02/AN02
PAD01/AN01
PAD00/AN00
VSS2
VDD2
PA7/ADDR15/DATA15
PA6/ADDR14/DATA14
PA5/ADDR13/DATA13
PA4/ADDR12/DATA12
PA3/ADDR11/DATA11
PA2/ADDR10/DATA10
PA1/ADDR9/DATA9
PA0/ADDR8/DATA8

PP4/KWP4/PWM4

PP5/KWP5/PWM5

PP7/KWP7/PWM7

VDDX

VSSX

PM0/RXCAN0/RXB

PM1/TXCAN0/TXB

PM2/RXCAN1/RXCAN0/MISO0

PM3/TXCAN1/TXCAN0/

SS0

PM4/RXCAN0/RXCAN4/MOSI0

PM5/TXCAN0/TXCAN4/SCK0

PJ6/KWJ6/RXCAN4/SD

PJ7/KWJ7/TXCAN4/SCL

VREGEN

PS3/TXD1

PS2/RXD1

PS1/TXD0

PS0/RXD0

VSSA

VRL

SS1/PWM3/KWP3/PP3

SCK1/PWM2/KWP2/PP2

MOSI1/PWM1/KWP1/PP1
MISO1/PWM0/KWP0/PP0

IOC0/PT0
IOC1/PT1
IOC2/PT2
IOC3/PT3

VDD1

VSS1

IOC4/PT4
IOC5/PT5
IOC6/PT6
IOC7/PT7

MODC/TAGHI/BKGD

ADDR0/DATA0/PB0
ADDR1/DATA1/PB1
ADDR2/DATA2/PB2
ADDR3/DATA3/PB3
ADDR4/DATA4/PB4

ADDR5/D

A
T
A5/PB5

ADDR6/D

A
T
A6/PB6

ADDR7/D

A
T
A7/PB7

XCLKS/NO

CC/PE7

MODB/IPIPE1/PE6

MOD

A/IPIPE0/PE5

ECLK/PE4

VSSR

VDDR

RESET

VDDPLL

XFC

VSSPLL

EXT

TEST

LSTRB/

T
A

GLO/PE3

W/PE2

IRQ/PE1

XIRQ/PE0

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

MC9S12DT128B Device User Guide -- V01.07

2.2 Signal Properties Summary

Table 2-1

summarizes the pin functionality. Signals shown in bold are not available in the 80 pin

package.

Table 2-1 Signal Properties

Pin Name

Function 1

Pin Name

Function 2

Pin Name

Function 3

Pin Name

Function 4

Pin Name

Function 5

Powered

Internal Pull

Resistor

Description

CTRL

Reset

State

EXTAL

VDDPLL

Oscillator Pins

XTAL

VDDPLL

RESET

VDDR

None

External Reset

TEST

N.A.

None

Test Input

VREGEN

VDDX

Voltage Regulator
Enable Input

XFC

VDDPLL

PLL Loop Filter

BKGD

TAGHI

MODC

VDDR

Always

Background Debug,
Tag High, Mode Input

PAD[15]

AN1[7]

ETRIG1

VDDA

None

Port AD Input,
Analog Inputs,
External Trigger
Input (ATD1)

PAD[14:8]

AN1[6:0]

VDDA

None

Port AD Input,
Analog Inputs
(ATD1)

PAD[7]

AN0[7]

ETRIG0

VDDA

None

Port AD Input, Analog
Inputs, External
Trigger Input (ATD0)

PAD[6:0]

AN0[6:0]

VDDA

None

Port AD Input, Analog
Inputs (ATD0)

PA[7:0]

ADDR[15:8]/

DATA[15:8]

VDDR

PUCR/

PUPAE

Disabled

Port A I/O,
Multiplexed
Address/Data

PB[7:0]

ADDR[7:0]/

DATA[7:0]

VDDR

PUCR/

PUPBE

Disabled

Port B I/O,
Multiplexed
Address/Data

PE7

NOACC

XCLKS

VDDR

PUCR/

PUPEE

Port E I/O, Access,
Clock Select

PE6

IPIPE1

MODB

VDDR

While RESET pin

low:

Down

Port E I/O, Pipe
Status, Mode Input

PE5

IPIPE0

MODA

VDDR

Port E I/O, Pipe
Status, Mode Input

PE4

ECLK

VDDR

PUCR/

PUPEE

Port E I/O, Bus Clock
Output

PE3

LSTRB

TAGLO

VDDR

PUCR/

PUPEE

Port E I/O, Byte
Strobe, Tag Low

PE2

R/W

VDDR

PUCR/

PUPEE

Port E I/O, R/W in
expanded modes

MC9S12DT128B Device User Guide -- V01.07

PE1

IRQ

VDDR

Always

Port E Input,
Maskable Interrupt

PE0

XIRQ

VDDR

Always

Port E Input, Non
Maskable Interrupt

PH7

KWH7

---

VDDR

PERH/

PPSH

Disabled Port H I/O, Interrupt

PH6

KWH6

---

VDDR

PERH/

PPSH

Disabled Port H I/O, Interrupt

PH5

KWH5

---

VDDR

PERH/

PPSH

Disabled Port H I/O, Interrupt

PH4

KWH4

---

VDDR

PERH/

PPSH

Disabled Port H I/O, Interrupt

PH3

KWH3

SS1

VDDR

PERH/

PPSH

Disabled

Port H I/O, Interrupt,
SS of SPI1

PH2

KWH2

SCK1

VDDR

PERH/

PPSH

Disabled

Port H I/O, Interrupt,
SCK of SPI1

PH1

KWH1

MOSI1

VDDR

PERH/

PPSH

Disabled

Port H I/O, Interrupt,
MOSI of SPI1

PH0

KWH0

MISO1

VDDR

PERH/

PPSH

Disabled

Port H I/O, Interrupt,
MISO of SPI1

PJ7

KWJ7

TXCAN4

SCL

VDDX

PERJ/

PPSJ

Port J I/O, Interrupt,
TX of CAN4, SCL of
IIC

PJ6

KWJ6

RXCAN4

SDA

VDDX

PERJ/

PPSJ

Port J I/O, Interrupt,
RX of CAN4, SDA of
IIC

PJ[1:0]

KWJ[1:0]

VDDX

PERJ/

PPSJ

Port J I/O, Interrupts

PK7

ECS

ROMCTL

VDDX

PUCR/

PUPKE

Port K I/O,
Emulation Chip
Select, ROM Control

PK[5:0]

XADDR[19:

14]

VDDX

PUCR/

PUPKE

Port K I/O, Extended
Addresses

PM7

BF_PSLM

TXCAN4

VDDX

PERM/

PPSM

Disabled

Port M I/O, BF slot
mismatch pulse, TX
of CAN4

PM6

BF_PERR

RXCAN4

VDDX

PERM/

PPSM

Disabled

Port M I/O, BF illegal
pulse/message
format error pulse,
RX of CAN4

PM5

BF_PROK

TXCAN0

TXCAN4

SCK0

VDDX

PERM/

PPSM

Disabled

Port M I/O, BF
reception ok pulse,
TX of CAN0, CAN4,
SCK of SPI0

PM4

BF_PSYN

RXCAN0

RXCAN4

MOSI0

VDDX

PERM/

PPSM

Disabled

Port M I/O, BF sync
pulse (Rx/Tx) OK
pulse o/p, RX of
CAN0, CAN4, MOSI
of SPI0

Pin Name

Function 1

Pin Name

Function 2

Pin Name

Function 3

Pin Name

Function 4

Pin Name

Function 5

Powered

Internal Pull

Resistor

Description

CTRL

Reset

State

MC9S12DT128B Device User Guide -- V01.07

PM3

TX_BF

TXCAN1

TXCAN0

SS0

VDDX

PERM/

PPSM

Disabled

Port M I/O, TX of BF,
CAN1, CAN0, SS of
SPI0

PM2

RX_BF

RXCAN1

RXCAN0

MISO0

VDDX

PERM/

PPSM

Disabled

Port M I/O, RX of BF,
CAN1, CAN0, MISO
of SPI0

PM1

TXCAN0

TXB

VDDX

PERM/

PPSM

Disabled

Port M I/O, TX of
CAN0, RX of BDLC

PM0

RXCAN0

RXB

VDDX

PERM/

PPSM

Disabled

Port M I/O, RX of
CAN0, RX of BDLC

PP7

KWP7

PWM7

VDDX

PERP/

PPSP

Disabled

Port P I/O, Interrupt,
Channel 7 of PWM

PP6

KWP6

PWM6

VDDX

PERP/

PPSP

Disabled

Port P I/O, Interrupt,
Channel 6 of PWM

PP5

KWP5

PWM5

VDDX

PERP/

PPSP

Disabled

Port P I/O, Interrupt,
Channel 5 of PWM

PP4

KWP4

PWM4

VDDX

PERP/

PPSP

Disabled

Port P I/O, Interrupt,
Channel 4 of PWM

PP3

KWP3

PWM3

SS1

VDDX

PERP/

PPSP

Disabled

Port P I/O, Interrupt,
Channel 3 of PWM,
SS of SPI1

PP2

KWP2

PWM2

SCK1

VDDX

PERP/

PPSP

Disabled

Port P I/O, Interrupt,
Channel 2 of PWM,
SCK of SPI1

PP1

KWP1

PWM1

MOSI1

VDDX

PERP/

PPSP

Disabled

Port P I/O, Interrupt,
Channel 1 of PWM,
MOSI of SPI1

PP0

KWP0

PWM0

MISO1

VDDX

PERP/

PPSP

Disabled

Port P I/O, Interrupt,
Channel 0 of PWM,
MISO2 of SPI1

PS7

SS0

VDDX

PERS/

PPSS

Port S I/O, SS of
SPI0

PS6

SCK0

VDDX

PERS/

PPSS

Port S I/O, SCK of
SPI0

PS5

MOSI0

VDDX

PERS/

PPSS

Port S I/O, MOSI of
SPI0

PS4

MISO0

VDDX

PERS/

PPSS

Port S I/O, MISO of
SPI0

PS3

TXD1

VDDX

PERS/

PPSS

Port S I/O, TXD of
SCI1

PS2

RXD1

VDDX

PERS/

PPSS

Port S I/O, RXD of
SCI1

PS1

TXD0

VDDX

PERS/

PPSS

Port S I/O, TXD of
SCI0

PS0

RXD0

VDDX

PERS/

PPSS

Port S I/O, RXD of
SCI0

PT[7:0]

IOC[7:0]

VDDX

PERT/

PPST

Disabled

Port T I/O, Timer
channels

Pin Name

Function 1

Pin Name

Function 2

Pin Name

Function 3

Pin Name

Function 4

Pin Name

Function 5

Powered

Internal Pull

Resistor

Description

CTRL

Reset

State

MC9S12DT128B Device User Guide -- V01.07

2.3 Detailed Signal Descriptions

2.3.1 EXTAL, XTAL -- Oscillator Pins

EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.

2.3.2 RESET -- External Reset Pin

An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up
state, and an output when an internal MCU function causes a reset.

2.3.3 TEST -- Test Pin

This input only pin is reserved for test.

NOTE:

The TEST pin must be tied to VSS in all applications.

2.3.4 XFC -- PLL Loop Filter Pin

PLL loop filter. Please ask your Motorola representative for the interactive application note to compute
PLL loop filter elements. Any current leakage on this pin must be avoided.

Figure 2-3 PLL Loop Filter Connections

2.3.5 BKGD / TAGHI / MODC -- Background Debug, Tag High, and Mode Pin

The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug
communication. In MCU expanded modes of operation when instruction tagging is on, an input low on
this pin during the falling edge of E-clock tags the high half of the instruction word being read into the
instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is
latched to the MODC bit at the rising edge of RESET. This pin has a permanently enabled pull-up device.

MCU

XFC

VDDPLL

MC9S12DT128B Device User Guide -- V01.07

2.3.6 PAD[15] / AN1[7] / ETRIG1 -- Port AD Input Pin [15]

PAD15 is a general purpose input pin and analog input of the analog to digital converter ATD1. It can act
as an external trigger input for the ATD1.

2.3.7 PAD[14:8] / AN1[6:0] -- Port AD Input Pins [14:8]

PAD14 - PAD8 are general purpose input pins and analog inputs of the analog to digital converter ATD1.

2.3.8 PAD[7] / AN0[7] / ETRIG0 -- Port AD Input Pin [7]

PAD7 is a general purpose input pin and analog input of the analog to digital converter ATD0. It can act
as an external trigger input for the ATD0.

2.3.9 PAD[6:0] / AN0[6:0] -- Port AD Input Pins [6:0]

PAD6 - PAD8 are general purpose input pins and analog inputs of the analog to digital converter ATD0.

2.3.10 PA[7:0] / ADDR[15:8] / DATA[15:8] -- Port A I/O Pins

PA7-PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.

2.3.11 PB[7:0] / ADDR[7:0] / DATA[7:0] -- Port B I/O Pins

PB7-PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.

2.3.12 PE7 / NOACC / XCLKS -- Port E I/O Pin 7

PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC
signal, when enabled, is used to indicate that the current bus cycle is an unused or "free" cycle. This signal
will assert when the CPU is not using the bus.
The XCLKS is an input signal which controls whether a crystal in combination with the internal Colpitts
(low power) oscillator is used or whether Pierce oscillator/external clock circuitry is used. The state of this
pin is latched at the rising edge of RESET. If the input is a logic low the EXTAL pin is configured for an
external clock drive. If input is a logic high an oscillator circuit is configured on EXTAL and XTAL. Since
this pin is an input with a pull-up device during reset, if the pin is left floating, the default configuration is
an oscillator circuit on EXTAL and XTAL.

MC9S12DT128B Device User Guide -- V01.07

2.3.13 PE6 / MODB / IPIPE1 -- Port E I/O Pin 6

PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE1. This pin is an input with a pull-down device which is only active
when RESET is low.

2.3.14 PE5 / MODA / IPIPE0 -- Port E I/O Pin 5

PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE0. This pin is an input with a pull-down device which is only active
when RESET is low.

2.3.15 PE4 / ECLK -- Port E I/O Pin 4

PE4 is a general purpose input or output pin. It can be configured to drive the internal bus clock ECLK.
ECLK can be used as a timing reference.

2.3.16 PE3 / LSTRB / TAGLO -- Port E I/O Pin 3

PE3 is a general purpose input or output pin. In MCU expanded modes of operation, LSTRB can be used
for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on,
TAGLO is used to tag the low half of the instruction word being read into the instruction queue.

2.3.17 PE2 / R/W -- Port E I/O Pin 2

PE2 is a general purpose input or output pin. In MCU expanded modes of operations, this pin drives the
read/write output signal for the external bus. It indicates the direction of data on the external bus.

2.3.18 PE1 / IRQ -- Port E Input Pin 1

PE1 is a general purpose input pin and the maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.

2.3.19 PE0 / XIRQ -- Port E Input Pin 0

PE0 is a general purpose input pin and the non-maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.

2.3.20 PH7 / KWH7 -- Port H I/O Pin 7

PH7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode.

MC9S12DT128B Device User Guide -- V01.07

2.3.21 PH6 / KWH6 -- Port H I/O Pin 6

PH6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode.

2.3.22 PH5 / KWH5 -- Port H I/O Pin 5

PH5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode.

2.3.23 PH4 / KWH4 -- Port H I/O Pin 2

PH4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode.

2.3.24 PH3 / KWH3 / SS1 -- Port H I/O Pin 3

PH3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as slave select pin SS of the Serial Peripheral Interface
1 (SPI1).

2.3.25 PH2 / KWH2 / SCK1 -- Port H I/O Pin 2

PH2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as serial clock pin SCK of the Serial Peripheral Interface
1 (SPI1).

2.3.26 PH1 / KWH1 / MOSI1 -- Port H I/O Pin 1

PH1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input
pin (during slave mode) MOSI of the Serial Peripheral Interface 1 (SPI1).

2.3.27 PH0 / KWH0 / MISO1 -- Port H I/O Pin 0

PH0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output
(during slave mode) pin MISO of the Serial Peripheral Interface 1 (SPI1).

2.3.28 PJ7 / KWJ7 / TXCAN4 / SCL -- PORT J I/O Pin 7

PJ7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as the transmit pin TXCAN for the Motorola Scalable
Controller Area Network controller 4 (CAN4) or the serial clock pin SCL of the IIC module.

MC9S12DT128B Device User Guide -- V01.07

2.3.29 PJ6 / KWJ6 / RXCAN4 / SDA -- PORT J I/O Pin 6

PJ6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as the receive pin RXCAN for the Motorola Scalable
Controller Area Network controller 4 (CAN4) or the serial data pin SDA of the IIC module.

2.3.30 PJ[1:0] / KWJ[1:0] -- Port J I/O Pins [1:0]

PJ1 and PJ0 are general purpose input or output pins. They can be configured to generate an interrupt
causing the MCU to exit STOP or WAIT mode.

2.3.31 PK7 / ECS / ROMCTL -- Port K I/O Pin 7

PK7 is a general purpose input or output pin. During MCU expanded modes of operation, this pin is used
as the emulation chip select output (ECS). During MCU expanded modes of operation, this pin is used to
enable the Flash EEPROM memory in the memory map (ROMCTL). At the rising edge of RESET, the
state of this pin is latched to the ROMON bit. For a complete list of modes refer to 4.2 Chip Configuration
Summary.

2.3.32 PK[5:0] / XADDR[19:14] -- Port K I/O Pins [5:0]

PK5-PK0 are general purpose input or output pins. In MCU expanded modes of operation, these pins
provide the expanded address XADDR[19:14] for the external bus.

2.3.33 PM7 / BF_PSLM / TXCAN4 -- Port M I/O Pin 7

PM7 is a general purpose input or output pin. It can be configured as the slot mismatch output pulse pin
of Byteflight. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area
Network controllers 4 (CAN4).

2.3.34 PM6 / BF_PERR / RXCAN4 -- Port M I/O Pin 6

PM6 is a general purpose input or output pin. It can be configured as the illegal pulse or message format
error output pulse pin of Byteflight. It can be configured as the receive pin RXCAN of the Motorola
Scalable Controller Area Network controllers 4 (CAN4).

2.3.35 PM5 / BF_PROK / TXCAN0 / TXCAN4 / SCK0 -- Port M I/O Pin 5

PM5 is a general purpose input or output pin. It can be configured as the reception OK output pulse pin of
Byteflight. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area
Network controllers 0 or 4 (CAN0 or CAN4). It can be configured as the serial clock pin SCK of the Serial
Peripheral Interface 0 (SPI0).

MC9S12DT128B Device User Guide -- V01.07

2.3.36 PM4 / BF_PSYN / RXCAN0 / RXCAN4/ MOSI0 -- Port M I/O Pin 4

PM4 is a general purpose input or output pin. It can be configured as the correct synchronisation pulse
reception/transmission output pulse pin of Byteflight. It can be configured as the receive pin RXCAN of
the Motorola Scalable Controller Area Network controllers 0 or 4 (CAN0 or CAN4). It can be configured
as the master output (during master mode) or slave input pin (during slave mode) MOSI for the Serial
Peripheral Interface 0 (SPI0).

2.3.37 PM3 / TX_BF / TXCAN1 / TXCAN0 / SS0 -- Port M I/O Pin 3

PM3 is a general purpose input or output pin. It can be configured as the transmit pinTX_BF of Byteflight.
It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network
controllers 1 or 0 (CAN1 or CAN0). It can be configured as the slave select pin SS of the Serial Peripheral
Interface 0 (SPI0).

2.3.38 PM2 / RX_BF / RXCAN1 / RXCAN0 / MISO0 -- Port M I/O Pin 2

PM2 is a general purpose input or output pin. It can be configured as the receive pin RX_BF of Byteflight.
It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network
controllers 1 or 0 (CAN1 or CAN0). It can be configured as the master input (during master mode) or slave
output pin (during slave mode) MISO for the Serial Peripheral Interface 0 (SPI0).

2.3.39 PM1 / TXCAN0 / TXB -- Port M I/O Pin 1

PM1 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the
Motorola Scalable Controller Area Network controller 0 (CAN0). It can be configured as the transmit pin
TXB of the BDLC.

2.3.40 PM0 / RXCAN0 / RXB -- Port M I/O Pin 0

PM0 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the
Motorola Scalable Controller Area Network controller 0 (CAN0). It can be configured as the receive pin
RXB of the BDLC.

2.3.41 PP7 / KWP7 / PWM7 -- Port P I/O Pin 7

PP7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 7 output.

2.3.42 PP6 / KWP6 / PWM6 -- Port P I/O Pin 6

PP6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 6 output.

MC9S12DT128B Device User Guide -- V01.07

2.3.43 PP5 / KWP5 / PWM5 -- Port P I/O Pin 5

PP5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 5 output.

2.3.44 PP4 / KWP4 / PWM4 -- Port P I/O Pin 4

PP4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 4 output.

2.3.45 PP3 / KWP3 / PWM3 / SS1 -- Port P I/O Pin 3

PP3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 3 output. It
can be configured as slave select pin SS of the Serial Peripheral Interface 1 (SPI1).

2.3.46 PP2 / KWP2 / PWM2 / SCK1 -- Port P I/O Pin 2

PP2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 2 output. It
can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 (SPI1).

2.3.47 PP1 / KWP1 / PWM1 / MOSI1 -- Port P I/O Pin 1

PP1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 1 output. It
can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of
the Serial Peripheral Interface 1 (SPI1).

2.3.48 PP0 / KWP0 / PWM0 / MISO1 -- Port P I/O Pin 0

PP0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 0 output. It
can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of
the Serial Peripheral Interface 1 (SPI1).

2.3.49 PS7 / SS0 -- Port S I/O Pin 7

PS7 is a general purpose input or output pin. It can be configured as the slave select pin SS of the Serial
Peripheral Interface 0 (SPI0).

2.3.50 PS6 / SCK0 -- Port S I/O Pin 6

PS6 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial
Peripheral Interface 0 (SPI0).

MC9S12DT128B Device User Guide -- V01.07

2.3.51 PS5 / MOSI0 -- Port S I/O Pin 5

PS5 is a general purpose input or output pin. It can be configured as master output (during master mode)
or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).

2.3.52 PS4 / MISO0 -- Port S I/O Pin 4

PS4 is a general purpose input or output pin. It can be configured as master input (during master mode) or
slave output pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).

2.3.53 PS3 / TXD1 -- Port S I/O Pin 3

PS3 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial
Communication Interface 1 (SCI1).

2.3.54 PS2 / RXD1 -- Port S I/O Pin 2

PS2 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial
Communication Interface 1 (SCI1).

2.3.55 PS1 / TXD0 -- Port S I/O Pin 1

PS1 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial
Communication Interface 0 (SCI0).

2.3.56 PS0 / RXD0 -- Port S I/O Pin 0

PS0 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial
Communication Interface 0 (SCI0).

2.3.57 PT[7:0] / IOC[7:0] -- Port T I/O Pins [7:0]

PT7-PT0 are general purpose input or output pins. They can be configured as input capture or output
compare pins IOC7-IOC0 of the Enhanced Capture Timer (ECT).

2.4 Power Supply Pins

MC9S12DT128B power and ground pins are described below.

Table 2-2 MC9S12DT128B Power and Ground Connection Summary

Mnemonic

Pin Number

Nominal

Voltage

Description

112-pin QFP

VDD1, 2

13, 65

2.5V

Internal power and ground generated by internal regulator

VSS1, 2

14, 66

MC9S12DT128B Device User Guide -- V01.07

NOTE:

All VSS pins must be connected together in the application.

2.4.1 VDDX,VSSX -- Power & Ground Pins for I/O Drivers

External power and ground for I/O drivers. Because fast signal transitions place high, short-duration
current demands on the power supply, use bypass capacitors with high-frequency characteristics and place
them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are
loaded.

2.4.2 VDDR, VSSR -- Power & Ground Pins for I/O Drivers & for Internal
Voltage Regulator

External power and ground for I/O drivers and input to the internal voltage regulator. Because fast signal

transitions place high, short-duration current demands on the power supply, use bypass capacitors with
high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements
depend on how heavily the MCU pins are loaded.

2.4.3 VDD1, VDD2, VSS1, VSS2 -- Core Power Pins

Power is supplied to the MCU through VDD and VSS. Because fast signal transitions place high,
short-duration current demands on the power supply, use bypass capacitors with high-frequency
characteristics and place them as close to the MCU as possible. This 2.5V supply is derived from the
internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is
turned off, if VREGEN is tied to ground.

NOTE:

No load allowed except for bypass capacitors.

VDDR

5.0V

External power and ground, supply to pin drivers and internal

voltage regulator.

VSSR

VDDX

107

5.0V

External power and ground, supply to pin drivers.

VSSX

106

VDDA

5.0V

Operating voltage and ground for the analog-to-digital

converters and the reference for the internal voltage regulator,
allows the supply voltage to the A/D to be bypassed
independently.

VSSA

VRL

Reference voltages for the analog-to-digital converter.

VRH

5.0V

VDDPLL

2.5V

Provides operating voltage and ground for the Phased-Locked

Loop. This allows the supply voltage to the PLL to be
bypassed independently. Internal power and ground
generated by internal regulator.

VSSPLL

VREGEN

Internal Voltage Regulator enable/disable

Mnemonic

Pin Number

Nominal

Voltage

Description

112-pin QFP

MC9S12DT128B Device User Guide -- V01.07

2.4.4 VDDA, VSSA -- Power Supply Pins for ATD and VREG

VDDA, VSSA are the power supply and ground input pins for the voltage regulator and the analog to
digital converter. It also provides the reference for the internal voltage regulator. This allows the supply
voltage to the ATD and the reference voltage to be bypassed independently.

2.4.5 VRH, VRL -- ATD Reference Voltage Input Pins

VRH and VRL are the reference voltage input pins for the analog to digital converter.

2.4.6 VDDPLL, VSSPLL -- Power Supply Pins for PLL

Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the
supply voltage to the Oscillator and PLL to be bypassed independently.This 2.5V voltage is generated by
the internal voltage regulator.

NOTE:

No load allowed except for bypass capacitors.

2.4.7 VREGEN -- On Chip Voltage Regulator Enable

Enables the internal 5V to 2.5V voltage regulator. If this pin is tied low, VDD1,2 and VDDPLL must be
supplied externally.

MC9S12DT128B Device User Guide -- V01.07

Section 4 Modes of Operation

4.1 Overview

Eight possible modes determine the operating configuration of the MC9S12DT128B. Each mode has an
associated default memory map and external bus configuration controlled by a further pin.

Three low power modes exist for the device.

4.2 Chip Configuration Summary

The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset (

Table 4-1

). The MODC, MODB, and MODA bits in the MODE register show the current operating

mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA
pins are latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting
of the ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the
memory map. ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin
is latched into the ROMON bit in the MISC register on the rising edge of the reset signal.

For further explanation on the modes refer to the Core User Guide.

Table 4-1 Mode Selection

BKGD =

MODC

PE6 =

MODB

PE5 =

MODA

PK7 =

ROMCTL

ROMON

Bit

Mode Description

Special Single Chip, BDM allowed and ACTIVE. BDM is
allowed in all other modes but a serial command is
required to make BDM active.

Emulation Expanded Narrow, BDM allowed

Special Test (Expanded Wide), BDM allowed

Emulation Expanded Wide, BDM allowed

Normal Single Chip, BDM allowed

Normal Expanded Narrow, BDM allowed

Special Peripheral; BDM allowed but bus operations
would cause bus conflicts (must not be used)

Normal Expanded Wide, BDM allowed

Table 4-2 Clock Selection Based on PE7

PE7 = XCLKS

Description

Colpitts Oscillator selected

Pierce Oscillator/external clock selected

MC9S12DT128B Device User Guide -- V01.07

4.3 Security

The device will make available a security feature preventing the unauthorized read and write of the
memory contents. This feature allows:

Protection of the contents of FLASH,

Protection of the contents of EEPROM,

Operation in single-chip mode, No BDM possible

Operation from external memory with internal FLASH and EEPROM disabled.

The user must be reminded that part of the security must lie with the user's code. An extreme example
would be user's code that dumps the contents of the internal program. This code would defeat the purpose
of security. At the same time the user may also wish to put a back door in the user's program. An example
of this is the user downloads a key through the SCI which allows access to a programming routine that
updates parameters stored in EEPROM.

4.3.1 Securing the Microcontroller

Once the user has programmed the FLASH and EEPROM (if desired), the part can be secured by
programming the security bits located in the FLASH module. These non-volatile bits will keep the part
secured through resetting the part and through powering down the part.

The security byte resides in a portion of the Flash array.

Check the Flash Block User Guide for more details on the security configuration.

4.3.2 Operation of the Secured Microcontroller

4.3.2.1 Normal Single Chip Mode

This will be the most common usage of the secured part. Everything will appear the same as if the part was
not secured with the exception of BDM operation. The BDM operation will be blocked.

4.3.2.2 Executing from External Memory

The user may wish to execute from external space with a secured microcontroller. This is accomplished
by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM
operations will be blocked.

Table 4-3 Voltage Regulator VREGEN

VREGEN

Description

Internal Voltage Regulator enabled

Internal Voltage Regulator disabled, VDD1,2 and
VDDPLL must be supplied externally with 2.5V

MC9S12DT128B Device User Guide -- V01.07

4.3.3 Unsecuring the Microcontroller

In order to unsecure the microcontroller, the internal FLASH and EEPROM must be erased. This can be
done through an external program in expanded mode.

Once the user has erased the FLASH and EEPROM, the part can be reset into special single chip mode.
This invokes a program that verifies the erasure of the internal FLASH and EEPROM. Once this program
completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally
done through the BDM, but the user could also change to expanded mode (by writing the mode bits
through the BDM) and jumping to an external program (again through BDM commands). Note that if the
part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be
secured again.

4.4 Low Power Modes

The microcontroller features three main low power modes. Consult the respective Block User Guide for
information on the module behavior in Stop, Pseudo Stop, and Wait Mode. An important source of
information about the clock system is the Clock and Reset Generator User Guide (CRG).

4.4.1 Stop

Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static
mode. Wake up from this mode can be done via reset or external interrupts.

4.4.2 Pseudo Stop

This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running
and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are
turned off. This mode consumes more current than the full STOP mode, but the wake up time from this
mode is significantly shorter.

4.4.3 Wait

This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute
instructions. The internal CPU signals (address and databus) will be fully static. All peripherals stay active.
For further power consumption the peripherals can individually turn off their local clocks.

4.4.4 Run

Although this is not a low power mode, unused peripheral modules should not be enabled in order to save
power.

MC9S12DT128B Device User Guide -- V01.07

Section 5 Resets and Interrupts

5.1 Overview

Consult the Exception Processing section of the HCS12 Core User Guide for information on resets and
interrupts.

5.2 Vectors

5.2.1 Vector Table

Table 5-1

lists interrupt sources and vectors in default order of priority.

Table 5-1 Interrupt Vector Locations

Vector Address

Interrupt Source

CCR

Mask

Local Enable

HPRIO Value

to Elevate

$FFFE, $FFFF

Reset

None

$FFFC, $FFFD

Clock Monitor fail reset

None

COPCTL (CME, FCME)

$FFFA, $FFFB

COP failure reset

None

COP rate select

$FFF8, $FFF9

Unimplemented instruction trap

None

$FFF6, $FFF7

SWI

None

$FFF4, $FFF5

XIRQ / BF High prio Sync pulse intr

X-Bit

None / BFRIER (XSYNIE)

$FFF2, $FFF3

IRQ

I-Bit

INTCR (IRQEN)

$F2

$FFF0, $FFF1

Real Time Interrupt

I-Bit

CRGINT (RTIE)

$F0

$FFEE, $FFEF

Enhanced Capture Timer channel 0

I-Bit

TIE (C0I)

$EE

$FFEC, $FFED

Enhanced Capture Timer channel 1

I-Bit

TIE (C1I)

$EC

$FFEA, $FFEB

Enhanced Capture Timer channel 2

I-Bit

TIE (C2I)

$EA

$FFE8, $FFE9

Enhanced Capture Timer channel 3

I-Bit

TIE (C3I)

$E8

$FFE6, $FFE7

Enhanced Capture Timer channel 4

I-Bit

TIE (C4I)

$E6

$FFE4, $FFE5

Enhanced Capture Timer channel 5

I-Bit

TIE (C5I)

$E4

$FFE2, $FFE3

Enhanced Capture Timer channel 6

I-Bit

TIE (C6I)

$E2

$FFE0, $FFE1

Enhanced Capture Timer channel 7

I-Bit

TIE (C7I)

$E0

$FFDE, $FFDF

Enhanced Capture Timer overflow

I-Bit

TSCR2 (TOF)

$DE

$FFDC, $FFDD

Pulse accumulator A overflow

I-Bit

PACTL (PAOVI)

$DC

$FFDA, $FFDB

Pulse accumulator input edge

I-Bit

PACTL (PAI)

$DA

$FFD8, $FFD9

SPI0

I-Bit

SP0CR1 (SPIE, SPTIE)

$D8

$FFD6, $FFD7

SCI0

I-Bit

SC0CR2

(TIE, TCIE, RIE, ILIE)

$D6

$FFD4, $FFD5

SCI1

I-Bit

SC1CR2

(TIE, TCIE, RIE, ILIE)

$D4

$FFD2, $FFD3

ATD0

I-Bit

ATD0CTL2 (ASCIE)

$D2

$FFD0, $FFD1

ATD1

I-Bit

ATD1CTL2 (ASCIE)

$D0

$FFCE, $FFCF

Port J

I-Bit

PTJIF (PTJIE)

$CE

$FFCC, $FFCD

Port H

I-Bit

PTHIF (PTHIE)

$CC

$FFCA, $FFCB

Modulus Down Counter underflow

I-Bit

MCCTL (MCZI)

$CA

MC9S12DT128B Device User Guide -- V01.07

5.3 Effects of Reset

When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module Block User Guides for register reset states.

5.3.1 I/O pins

Refer to the HCS12 Core User Guides for mode dependent pin configuration of port A, B, E and K out of
reset.

Refer to the PIM Block User Guide for reset configurations of all peripheral module ports.

$FFC8, $FFC9

Pulse Accumulator B Overflow

I-Bit

PBCTL (PBOVI)

$C8

$FFC6, $FFC7

CRG PLL lock

I-Bit

PLLCR (LOCKIE)

$C6

$FFC4, $FFC5

CRG Self Clock Mode

I-Bit

PLLCR (SCMIE)

$C4

$FFC2, $FFC3

BDLC

I-Bit

DLCBCR1 (IE)

$C2

$FFC0, $FFC1

IIC Bus

I-Bit

IBCR (IBIE)

$C0

$FFBE, $FFBF

SPI1

I-Bit

SP1CR1 (SPIE, SPTIE)

$BE

$FFBC, $FFBD

Reserved

$FFBA, $FFBB

EEPROM

I-Bit

ECNFG (CCIE, CBEIE)

$BA

$FFB8, $FFB9

FLASH

I-Bit

FCNFG (CCIE, CBEIE)

$B8

$FFB6, $FFB7

CAN0 wake-up

I-Bit

CAN0RIER (WUPIE)

$B6

$FFB4, $FFB5

CAN0 errors

I-Bit

CAN0RIER (CSCIE, OVRIE)

$B4

$FFB2, $FFB3

CAN0 receive

I-Bit

CAN0RIER (RXFIE)

$B2

$FFB0, $FFB1

CAN0 transmit

I-Bit

CAN0TIER (TXEIE[2:0])

$B0

$FFAE, $FFAF

CAN1 wake-up

I-Bit

CAN1RIER (WUPIE)

$AE

$FFAC, $FFAD

CAN1 errors

I-Bit

CAN1RIER (CSCIE, OVRIE)

$AC

$FFAA, $FFAB

CAN1 receive

I-Bit

CAN1RIER (RXFIE)

$AA

$FFA8, $FFA9

CAN1 transmit

I-Bit

CAN1TIER (TXEIE[2:0])

$A8

$FFA6, $FFA7

BF Rx FIFO not empty

I-Bit

BFRIER (RCVFIE)

$A6

$FFA4, $FFA5

BF receive

I-Bit

BFBUFCTL[15:0] (IENA)

$A4

$FFA2, $FFA3

BF Synchronisation

I-Bit

BFRIER (SYNAIE, SYNNIE)

$A2

$FFA0, $FFA1

BF general

I-Bit

BFBUFCTL[15:0] (IENA),

BFGIER (OVRNIE, ERRIE,

SYNEIE, SYNLIE, ILLPIE,

LOCKIE, WAKEIE)
BFRIER (SLMMIE)

$A0

$FF98, $FF9F

Reserved

$FF96, $FF97

CAN4 wake-up

I-Bit

CAN4RIER (WUPIE)

$96

$FF94, $FF95

CAN4 errors

I-Bit

CAN4RIER (CSCIE, OVRIE)

$94

$FF92, $FF93

CAN4 receive

I-Bit

CAN4RIER (RXFIE)

$92

$FF90, $FF91

CAN4 transmit

I-Bit

CAN4TIER (TXEIE[2:0])

$90

$FF8E, $FF8F

Port P Interrupt

I-Bit

PTPIF (PIEP)

$8E

$FF8C, $FF8D

PWM Emergency Shutdown

I-Bit

PWMSDN (PWMIE)

$8C

$FF80 to
$FF8B

Reserved

MC9S12DT128B Device User Guide -- V01.07

Section 6 HCS12 Core Block Description

Consult the HCS12 Core User Guide for information about the HCS12 core modules, i.e. central
processing unit (CPU), interrupt module (INT), module mapping control module (MMC), multiplexed
external bus interface (MEBI), breakpoint module (BKP) and background debug mode module (BDM).

Section 7 Clock and Reset Generator (CRG) Block
Description

Consult the CRG Block User Guide for information about the Clock and Reset Generator module.

7.1 Device-specific information

7.1.1 XCLKS

The XCLKS input signal is active low (see 2.3.12 PE7 / NOACC / XCLKS -- Port E I/O Pin 7).

Section 8 Enhanced Capture Timer (ECT) Block
Description

Consult the ECT_16B8C Block User Guide for information about the Enhanced Capture Timer
module.When the ECT_16B8C Block User Guide refers to freeze mode this is equivalent to active BDM
mode.

Section 9 Analog to Digital Converter (ATD) Block
Description

There are two Analog to Digital Converters (ATD1 and ATD0) implemented on the MC9S12DT128B.
Consult the ATD_10B8C Block User Guide for information about each Analog to Digital Converter
module. When the ATD_10B8C Block User Guide refers to freeze mode this is equivalent to active BDM
mode.

Section 10 Inter-IC Bus (IIC) Block Description

Consult the IIC Block User Guide for information about the Inter-IC Bus module.

Section 11 Serial Communications Interface (SCI) Block

MC9S12DT128B Device User Guide -- V01.07

Description

There are two Serial Communications Interfaces (SCI1 and SCI0) implemented on theMC9S12DT128B
device. Consult the SCI Block User Guide for information about each Serial Communications Interface
module.

Section 12 Serial Peripheral Interface (SPI) Block
Description

There are two Serial Peripheral Interfaces (SPI1 and SPI0) implemented on MC9S12DT128B. Consult the
SPI Block User Guide for information about each Serial Peripheral Interface module.

Section 13 J1850 (BDLC) Block Description

Consult the BDLC Block User Guide for information about the J1850 module.

Section 14 Byteflight (BF) Block Description

Consult the BF Block User Guide for information about the 10 Mbps Byteflight module.

Section 15 Pulse Width Modulator (PWM) Block
Description

Consult the PWM_8B8C Block User Guide for information about the Pulse Width Modulator module.
When the PWM_8B8C Block User Guide refers to freeze mode this is equivalent to active BDM mode.

Section 16 Flash EEPROM 128K Block Description

Consult the FTS128K Block User Guide for information about the flash module.

Section 17 EEPROM 2K Block Description

Consult the EETS2K Block User Guide for information about the EEPROM module.

MC9S12DT128B Device User Guide -- V01.07

Section 22 Printed Circuit Board Layout Proposal

The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:

Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the
corresponding pins (C1 C6).

Central point of the ground star should be the VSSR pin.

Use low ohmic low inductance connections between VSS1, VSS2 and VSSR.

VSSPLL must be directly connected to VSSR.

Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7,
C8, C11 and Q1 as small as possible.

Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the
connection area to the MCU.

Central power input should be fed in at the VDDA/VSSA pins.

Table 22-1 Suggested External Component Values

Component

Purpose

Type

Value

VDD1 filter cap

ceramic X7R

100 ... 220nF

VDD2 filter cap

ceramic X7R

100 ... 220nF

VDDA filter cap

ceramic X7R

100nF

VDDR filter cap

X7R/tantalum

>= 100nF

VDDPLL filter cap

ceramic X7R

100nF

VDDX filter cap

X7R/tantalum

>= 100nF

OSC load cap

C9 / C

PLL loop filter cap

See PLL specification chapter

C10 / C

PLL loop filter cap

C11 / C

DC cutoff cap

Colpitts mode only, if recommended by

quartz manufacturer

R1 / R

PLL loop filter res

See PLL Specification chapter

R2 / R

Pierce mode only

R3 / R

Quartz

MC9S12DT128B Device User Guide -- V01.07

Appendix A Electrical Characteristics

A.1 General

This introduction is intended to give an overview on several common topics like power supply, current
injection etc.

A.1.1 Parameter Classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate.

Those parameters are guaranteed during production testing on each individual device.

Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations. They are regularly verified by production monitors.

Those parameters are achieved by design characterization on a small sample size from typical
devices. All values shown in the typical column are within this category.

Those parameters are derived mainly from simulations.

A.1.2 Power Supply

The MC9S12DT128B utilizes several pins to supply power to the I/O ports, A/D converter, oscillator and
PLL as well as the digital core.

The VDDA, VSSA pair supplies the A/D converter and the resistor ladder of the internal voltage regulator.

The VDDX, VSSX, VDDR and VSSR pairs supply the I/O pins ,VDDR supplies also the internal voltage
regulator.

VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the
oscillator and the PLL.

VSS1 and VSS2 are internally connected by metal.

VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD
protection.

MC9S12DT128B Device User Guide -- V01.07

NOTE:

In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5
is used for either VSSA, VSSR and VSSX unless otherwise noted.
IDD5 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR
pins.
VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and
VSSPLL.
IDD is used for the sum of the currents flowing into VDD1 and VDD2.

A.1.3 Pins

There are four groups of functional pins.

A.1.3.1 5V I/O pins

Those I/O pins have a nominal level of 5V. This class of pins is comprised of all port I/O pins, the analog
inputs, BKGD pin and the RESET inputs.The internal structure of all those pins is identical, however some
of the functionality may be disabled. E.g. for the analog inputs the output drivers, pull-up and pull-down
resistors are disabled permanently.

A.1.3.2 Analog Reference

This class is made up by the two VRH and VRL pins.

A.1.3.3 Oscillator

The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied
by VDDPLL.

A.1.3.4 TEST

This pin is used for production testing only.

A.1.3.5 VREGEN

This pin is used to enable the on chip voltage regulator.

A.1.4 Current Injection

Power supply must maintain regulation within operating V

DD5

or V

range during instantaneous and

operating maximum current conditions. If positive injection current (V

> V

DD5

) is greater than I

DD5

, the

injection current may flow out of VDD5 and could result in external power supply going out of regulation.
Insure external VDD5 load will shunt current greater than maximum injection current. This will be the
greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is
very low which would reduce overall power consumption.

MC9S12DT128B Device User Guide -- V01.07

A.1.5 Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima
is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the
device.

This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either V

SS5

or V

DD5

A.1.6 ESD Protection and Latch-up Immunity

All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model.

Table A-1 Absolute Maximum Ratings

NOTES

1. Beyond absolute maximum ratings device might be damaged.

Num

Rating

Symbol

Min

Max

Unit

I/O, Regulator and Analog Supply Voltage

DD5

-0.3

6.0

Digital Logic Supply Voltage

2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply.

The absolute maximum ratings apply when the device is powered from an external source.

-0.3

3.0

PLL Supply Voltage

DDPLL

-0.3

3.0

Voltage difference VDDX to VDDR and VDDA

VDDX

-0.3

0.3

Voltage difference VSSX to VSSR and VSSA

VSSX

-0.3

0.3

Digital I/O Input Voltage

-0.3

6.0

Analog Reference

RH,

-0.3

6.0

XFC, EXTAL, XTAL inputs

ILV

-0.3

3.0

TEST input

TEST

-0.3

10.0

Instantaneous Maximum Current

Single pin limit for all digital I/O pins

3. All digital I/O pins are internally clamped to V

SSX

and V

DDX

, V

SSR

and V

DDR

or V

SSA

and V

DDA

-25

+25

Instantaneous Maximum Current

Single pin limit for XFC, EXTAL, XTAL

4. Those pins are internally clamped to V

SSPLL

and V

DDPLL

-25

+25

Instantaneous Maximum Current

Single pin limit for TEST

5. This pin is clamped low to V

SSPLL

, but not clamped high. This pin must be tied low in applications.

-0.25

Storage Temperature Range

stg

155

MC9S12DT128B Device User Guide -- V01.07

A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.

A.1.7 Operating Conditions

This chapter describes the operating conditions of the device. Unless otherwise noted those conditions
apply to all the following data.

NOTE:

Please refer to the temperature rating of the device (C, V, M) with regards to the
ambient temperature T

and the junction temperature T

. For power dissipation

Table A-2 ESD and Latch-up Test Conditions

Model

Description

Symbol

Value

Unit

Human Body

Series Resistance

1500

Ohm

Storage Capacitance

100

Number of Pulse per pin
positive
negative

3
3

Machine

Series Resistance

Ohm

Storage Capacitance

200

Number of Pulse per pin
positive
negative

3
3

Latch-up

Minimum input voltage limit

2.5

Maximum input voltage limit

7.5

Table A-3 ESD and Latch-Up Protection Characteristics

Num

Rating

Symbol

Min

Max

Unit

C Human Body Model (HBM)

HBM

2000

C Machine Model (MM)

200

C Charge Device Model (CDM)

CDM

500

Latch-up Current at 125

positive
negative

LAT

+100
100

Latch-up Current at 27

positive
negative

LAT

+200
200

MC9S12DT128B Device User Guide -- V01.07

calculations refer to Section A.1.8 Power Dissipation and Thermal
Characteristics.

A.1.8 Power Dissipation and Thermal Characteristics

Power dissipation and thermal characteristics are closely related. The user must assure that the maximum
operating junction temperature is not exceeded. The average chip-junction temperature (T

) in

C can be

obtained from:

Table A-4 Operating Conditions

Rating

Symbol

Min

Typ

Max

Unit

I/O, Regulator and Analog Supply Voltage

DD5

4.5

5.25

Digital Logic Supply Voltage

NOTES

1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The

absolute maximum ratings apply when this regulator is disabled and the device is powered from an external
source.

2.35

2.5

2.75

PLL Supply Voltage

DDPLL

2.25

2.5

2.75

Voltage Difference VDDX to VDDR and VDDA

VDDX

-0.1

0.1

Voltage Difference VSSX to VSSR and VSSA

VSSX

-0.1

0.1

Oscillator

osc

0.5

MHz

Bus Frequency

bus

0.5

MHz

MC9S12DT128BC

Operating Junction Temperature Range

-40

100

Operating Ambient Temperature Range

2. Please refer to Section A.1.8 Power Dissipation and Thermal Characteristics for more details about the rela-

tion between ambient temperature T

and device junction temperature T

-40

MC9S12DT128BV

Operating Junction Temperature Range

-40

120

Operating Ambient Temperature Range

-40

105

MC9S12DT128BM

Operating Junction Temperature Range

-40

140

Operating Ambient Temperature Range

-40

125

(

)

Junction Temperature, [

]

Ambient Temperature, [

]

MC9S12DT128B Device User Guide -- V01.07

The total power dissipation can be calculated from:

Two cases with internal voltage regulator enabled and disabled must be considered:

Internal Voltage Regulator disabled

Which is the sum of all output currents on I/O ports associated with VDDX and VDDM.

For R

DSON

is valid:

respectively

Internal voltage regulator enabled

DDR

is the current shown in

Table A-7

and not the overall current flowing into VDDR, which

additionally contains the current flowing into the external loads with output high.

Which is the sum of all output currents on I/O ports associated with VDDX and VDDR.

Total Chip Power Dissipation, [W]

Package Thermal Resistance, [

C/W]

INT

Chip Internal Power Dissipation, [W]

INT

DDPLL

DDA

DSON

------------ for outputs driven low

;

DSON

DD5

------------------------------------ for outputs driven high

;

INT

DDR

DDA

DSON

MC9S12DT128B Device User Guide -- V01.07

A.1.9 I/O Characteristics

This section describes the characteristics of all 5V I/O pins. All parameters are not always applicable, e.g.
not all pins feature pull up/down resistances.

Table A-5 Thermal Package Characteristics

NOTES

1. The values for thermal resistance are achieved by package simulations

Num C

Rating

Symbol

Min

Typ

Max

Unit

T Thermal Resistance LQFP112, single sided PCB

2. PC Board according to EIA/JEDEC Standard 51-3

C/W

Thermal Resistance LQFP112, double sided PCB

with 2 internal planes

3. PC Board according to EIA/JEDEC Standard 51-7

C/W

T Junction to Board LQFP112

C/W

T Junction to Case LQFP112

C/W

T Junction to Package Top LQFP112

C/W

T Thermal Resistance QFP 80, single sided PCB

C/W

Thermal Resistance QFP 80, double sided PCB with
2 internal planes

C/W

T Junction to Board QFP80

C/W

T Junction to Case QFP80

C/W

T Junction to Package Top QFP80

C/W

MC9S12DT128B Device User Guide -- V01.07

Table A-6 5V I/O Characteristics

Conditions are shown in Table A-4 unless otherwise noted

Num C

Rating

Symbol

Min

Typ

Max

Unit

P Input High Voltage

0.65*V

DD5

T Input High Voltage

DD5

+ 0.3

P Input Low Voltage

0.35*V

DD5

T Input Low Voltage

SS5

0.3

C Input Hysteresis

HYS

250

Input Leakage Current (pins in high ohmic input

mode)

= V

DD5

or V

SS5

ADC Inputs AN15:0
All other Ports (A, B, E, K, M, S, T)

NOTES

1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for

each 8 C to 12 C in the temperature range from 50 C to 125 C.

-1.0

2.5

1.0
2.5

C
P

Output High Voltage (pins in output mode)

Partial Drive IOH = 2.0mA
Full Drive IOH = 10.0mA

DD5

0.8

C
P

Output Low Voltage (pins in output mode)

Partial Drive IOL = +2.0mA
Full Drive IOL = +10.0mA

0.8

Internal Pull Up Device Current,
tested at V

Max.

PUL

130

Internal Pull Up Device Current,
tested at V

Min.

PUH

Internal Pull Down Device Current,
tested at V

Min.

PDH

130

Internal Pull Down Device Current,
tested at V

Max.

PDL

D Input Capacitance

Injection current

Single Pin limit
Total Device Limit. Sum of all injected currents

2. Refer to Section A.1.4 Current Injection, for more details

ICS

ICP

2.5

P Port H, J, P Interrupt Input Pulse filtered

3. Parameter only applies in STOP or Pseudo STOP mode.

PULSE

P Port H, J, P Interrupt Input Pulse passed

PULSE

MC9S12DT128B Device User Guide -- V01.07

given. A very good estimate is to take the single chip currents and add the currents due to the external
loads.

Table A-7 Supply Current Characteristics

Conditions are shown in Table A-4 unless otherwise noted

Num C

Rating

Symbol

Min

Typ

Max

Unit

Run supply currents

Single Chip, Internal regulator enabled

DD5

P
P

Wait Supply current

All modules enabled, PLL on

only RTI enabled

DDW

C
P
C
C
P
C
P
C
P

Pseudo Stop Current (RTI and COP disabled)

1, 2

-40

"C" Temp Option 100

105

"V" Temp Option 120

125

"M" Temp Option 140

NOTES

1. PLL off, Oscillator in Colpitts Mode
2. At those low power dissipation levels T

= T

can be assumed

DDPS

370
400
450
550
600
650
800
850

1200

500

1600

2100

5000

C
C
C
C
C
C
C

Pseudo Stop Current (RTI and COP enabled)

1, 2

-40

105

125

140

DDPS

570
600
650
750
850

1200
1500

C
P
C
C
P
C
P
C
P

Stop Current

-40

"C" Temp Option 100

105

"V" Temp Option 120

125

"M" Temp Option 140

DDS

12
25

100
130
160
200
350
400
600

100

1200

1700

5000

MC9S12DT128B Device User Guide -- V01.07

A.2 ATD Characteristics

This section describes the characteristics of the analog to digital converter.

A.2.1 ATD Operating Characteristics

The

Table A-8

shows conditions under which the ATD operates.

The following constraints exist to obtain full-scale, full range results:
V

SSA

DDA

This constraint exists since the sample buffer amplifier can not drive

beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively
be clipped.

Table A-8 ATD Operating Characteristics

A.2.2 Factors influencing accuracy

Three factors source resistance, source capacitance and current injection have an influence on the
accuracy of the ATD.

A.2.2.1 Source Resistance:

Due to the input pin leakage current as specified in

Table A-6

in conjunction with the source resistance

there will be a voltage drop from the signal source to the ATD input. The maximum source resistance R

Conditions are shown in Table A-4 unless otherwise noted

Num C

Rating

Symbol

Min

Typ

Max

Unit

Reference Potential

Low

High

SSA

DDA

V
V

C Differential Reference Voltage

NOTES

1. Full accuracy is not guaranteed when differential voltage is less than 4.50V

-V

4.50

5.00

5.25

D ATD Clock Frequency

ATDCLK

0.5

2.0

MHz

ATD 10-Bit Conversion Period

Clock Cycles

Conv, Time at 2.0MHz ATD Clock f

ATDCLK

2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample

period of 16 ATD clocks.

CONV10

28
14

Cycles

ATD 8-Bit Conversion Period

Clock Cycles

(2)

Conv, Time at 2.0MHz ATD Clock f

ATDCLK

CONV8

26
13

Cycles

D Stop Recovery Time (V

DDA

=5.0 Volts)

P Reference Supply current (Both ATD modules on)

REF

0.75

P Reference Supply current (Only one ATD module on)

REF

0.375

MC9S12DT128B Device User Guide -- V01.07

specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or
operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source
resistance is allowed.

A.2.2.2 Source capacitance

When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due
to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input
voltage

1LSB, then the external filter capacitor, C

1024 * (C

INS

INN

A.2.2.3 Current injection

There are two cases to consider.

A current is injected into the channel being converted. The channel being stressed has conversion
values of $3FF ($FF in 8-bit mode) for analog inputs greater than V

and $000 for values less than

unless the current is higher than specified as disruptive conditions.

Current is injected into pins in the neighborhood of the channel being converted. A portion of this
current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy
of the conversion depending on the source resistance.
The additional input voltage error on the converted channel can be calculated as V

ERR

= K * R

INJ

, with I

INJ

being the sum of the currents injected into the two pins adjacent to the converted

channe

Table A-9 ATD Electrical Characteristics

Conditions are shown in Table A-4 unless otherwise noted

Num C

Rating

Symbol

Min

Typ

Max

Unit

C Max input Source Resistance

Total Input Capacitance
Non Sampling
Sampling

INN

INS

10
22

C Disruptive Analog Input Current

-2.5

2.5

C Coupling Ratio positive current injection

-4

A/A

C Coupling Ratio negative current injection

-2

A/A

MC9S12DT128B Device User Guide -- V01.07

A.2.3 ATD accuracy

Table A-10

specifies the ATD conversion performance excluding any errors due to current injection,

input capacitance and source resistance.

Table A-10 ATD Conversion Performance

For the following definitions see also

Figure A-1

Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.

The Integral Non-Linearity (INL) is defined as the sum of all DNLs:

Conditions are shown in Table A-4 unless otherwise noted
V

REF

= V

- V

= 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV

ATDCLK

= 2.0MHz

Num C

Rating

Symbol

Min

Typ

Max

Unit

P 10-Bit Resolution

LSB

P 10-Bit Differential Nonlinearity

DNL

Counts

P 10-Bit Integral Nonlinearity

INL

2.5

1.5

2.5

Counts

P 10-Bit Absolute Error

NOTES

1. These values include the quantization error which is inherently 1/2 count for any A/D converter.

-3

2.0

Counts

P 8-Bit Resolution

LSB

P 8-Bit Differential Nonlinearity

DNL

0.5

Counts

P 8-Bit Integral Nonlinearity

INL

1.0

0.5

1.0

Counts

P 8-Bit Absolute Error

(1)

-1.5

1.0

1.5

Counts

DNL i

( )

1LSB

------------------------

INL n

( )

DNL i

( )

1LSB

--------------------

MC9S12DT128B Device User Guide -- V01.07

A.3 NVM, Flash and EEPROM

NOTE:

Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for
both Flash and EEPROM.

A.3.1 NVM timing

The time base for all NVM program or erase operations is derived from the oscillator. A minimum
oscillator frequency f

NVMOSC

is required for performing program or erase operations. The NVM modules

do not have any means to monitor the frequency and will not prevent program or erase operation at
frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at
a lower frequency a full program or erase transition is not assured.

The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator
using the FCLKDIV and ECLKDIV registers respectively. The frequency of this clock must be set within
the limits specified as f

NVMOP

The minimum program and erase times shown in

Table A-11

are calculated for maximum f

NVMOP

and

maximum f

bus

. The maximum times are calculated for minimum f

NVMOP

and a f

bus

of 2MHz.

A.3.1.1 Single Word Programming

The programming time for single word programming is dependant on the bus frequency as a well as on
the frequency f¨

NVMOP

and can be calculated according to the following formula.

A.3.1.2 Burst Programming

This applies only to the Flash where up to 32 words in a row can be programmed consecutively using burst
programming by keeping the command pipeline filled. The time to program a consecutive word can be
calculated as:

The time to program a whole row is:

Burst programming is more than 2 times faster than single word programming.

swpgm

NVMOP

---------------------

bus

----------

bwpgm

NVMOP

---------------------

bus

----------

brpgm

swpgm

31 t

bwpgm

MC9S12DT128B Device User Guide -- V01.07

A.3.1.3 Sector Erase

Erasing a 512 byte Flash sector or a 4 byte EEPROM sector takes:

The setup times can be ignored for this operation.

A.3.1.4 Mass Erase

Erasing a NVM block takes:

The setup times can be ignored for this operation.

A.3.1.5 Blank Check

The time it takes to perform a blank check on the Flash or EEPROM is dependant on the location of the
first non-blank word starting at relative address zero. It takes one bus cycle per word to verify plus a setup
of the command.

Table A-11 NVM Timing Characteristics

Conditions are shown in Table A-4 unless otherwise noted

Num C

Rating

Symbol

Min

Typ

Max

Unit

D External Oscillator Clock

NVMOSC

0.5

NOTES

1. Restrictions for oscillator in crystal mode apply!

MHz

D Bus frequency for Programming or Erase Operations

NVMBUS

MHz

D Operating Frequency

NVMOP

150

200

kHz

P Single Word Programming Time

swpgm

2. Minimum Programming times are achieved under maximum NVM operating frequency f

NVMOP

and maximum bus frequency

bus

74.5

3. Maximum Erase and Programming times are achieved under particular combinations of f

NVMOP

and bus frequency f

bus

Refer to formulae in Sections A.3.1.1 - A.3.1.5 for guidance.

D Flash Burst Programming consecutive word

bwpgm

20.4

D Flash Burst Programming Time for 32 Words

brpgm

678.4

1035.5

P Sector Erase Time

era

26.7

P Mass Erase Time

mass

100

133

D Blank Check Time Flash per block

check

32778

cyc

D Blank Check Time EEPROM per block

check

2058

cyc

era

4000

NVMOP

---------------------

mass

20000

NVMOP

---------------------

check

location t

cyc

10 t

cyc

MC9S12DT128B Device User Guide -- V01.07

A.3.2 NVM Reliability

The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process
monitors and burn-in to screen early life failures.

The failure rates for data retention and program/erase cycling are specified at the operating conditions
noted.

The program/erase cycle count on the sector is incremented every time a sector or mass erase event is
executed.

NOTE:

All values shown in

Table A-12

are target values and subject to further extensive

characterization

Table A-12 NVM Reliability Characteristics

NOTE:

Flash cycling performance is 10 cycles at -40°C to +125°C. Data retention is
specified for 15 years.

NOTE:

EEPROM cycling performance is 10K cycles at -40°C to 125°C. Data retention is
specified for 5 years on words after cycling 10K times. However if only 10 cycles
are executed on a word the data retention is specified for 15 years.

4. Burst Programming operations are not applicable to EEPROM
5. Minimum Erase times are achieved under maximum NVM operating frequency f

NVMOP

6. Minimum time, if first word in the array is not blank
7. Maximum time to complete check on an erased block

Conditions are shown in Table A-4 unless otherwise noted

Num C

Rating

Cycles

Data Retention

Lifetime

Unit

C Flash/EEPROM (-40°C to +125°C)

Years

C EEPROM (-40°C to +125°C)

10,000

Years

MC9S12DT128B Device User Guide -- V01.07

103

A.5 Reset, Oscillator and PLL

This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).

A.5.1 Startup

Table A-14

summarizes several startup characteristics explained in this section. Detailed description of

the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.

Table A-14 Startup Characteristics

A.5.1.1 POR

The release level V

PORR

and the assert level V

PORA

are derived from the V

Supply. They are also valid

if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time t

CQOUT

no valid oscillation is detected, the MCU will start using the internal self

clock. The fastest startup time possible is given by n

uposc

A.5.1.2 SRAM Data Retention

Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.

A.5.1.3 External Reset

When external reset is asserted for a time greater than PW

RSTL

the CRG module generates an internal

reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.

A.5.1.4 Stop Recovery

Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR
is performed before releasing the clocks to the system.

Conditions are shown in Table A-4 unless otherwise noted

Num C

Rating

Symbol

Min

Typ

Max

Unit

T POR release level

PORR

2.07

T POR assert level

PORA

0.97

D Reset input pulse width, minimum input time

RSTL

osc

D Startup from Reset

RST

192

196

osc

D Interrupt pulse width, IRQ edge-sensitive mode

IRQ

D Wait recovery startup time

WRS

cyc

MC9S12DT128B Device User Guide -- V01.07

104

A.5.1.5 Pseudo Stop and Wait Recovery

The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in
both modes. The controller can be woken up by internal or external interrupts. After t

wrs

the CPU starts

fetching the interrupt vector.

A.5.2 Oscillator

The device features an internal Colpitts and Pierce oscillator. The selection of Colpitts oscillator or Pierce
oscillator/external clock depends on the XCLKS signal which is sampled during reset.By asserting the
XCLKS input during reset this oscillator can be bypassed allowing the input of a square wave. Before
asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start
from either power-on, STOP or oscillator fail. t

CQOUT

specifies the maximum time before switching to the

internal self clock mode after POR or STOP if a proper oscillation is not detected. The quality check also
determines the minimum oscillator start-up time t

UPOSC

. The device also features a clock monitor. A

Clock Monitor Failure is asserted if the frequency of the incoming clock signal is below the Assert
Frequency f

CMFA.

Table A-15 Oscillator Characteristics

Conditions are shown in Table A-4 unless otherwise noted

Num C

Rating

Symbol

Min

Typ

Max

Unit

C Crystal oscillator range (Colpitts)

OSC

0.5

MHz

C Crystal oscillator range (Pierce)

NOTES

1. Depending on the crystal a damping series resistor might be necessary

OSC

0.5

MHz

P Startup Current

OSC

100

C Oscillator start-up time (Colpitts)

UPOSC

2. f

osc

= 4MHz, C = 22pF.

100

3. Maximum value is for extreme cases using high Q, low frequency crystals

D Clock Quality check time-out

CQOUT

0.45

2.5

P Clock Monitor Failure Assert Frequency

CMFA

100

200

KHz

P External square wave input frequency

4. XCLKS =0 during reset

EXT

0.5

MHz

D External square wave pulse width low

EXTL

9.5

D External square wave pulse width high

EXTH

9.5

D External square wave rise time

EXTR

D External square wave fall time

EXTF

D Input Capacitance (EXTAL, XTAL pins)

DC Operating Bias in Colpitts Configuration on
EXTAL Pin

DCBIAS

1.1

MC9S12DT128B Device User Guide -- V01.07

105

A.5.3 Phase Locked Loop

The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO)
is also the system clock source in self clock mode.

A.5.3.1 XFC Component Selection

This section describes the selection of the XFC components to achieve a good filter characteristics.

Figure A-2 Basic PLL functional diagram

The following procedure can be used to calculate the resistance and capacitance values using typical
values for K

, f

and i

from

Table A-16

The grey boxes show the calculation for f

VCO

= 50MHz and f

ref

= 1MHz. E.g., these frequencies are used

for f

OSC

= 4MHz and a 25MHz bus clock.

The VCO Gain at the desired VCO frequency is approximated by:

The phase detector relationship is given by:

is the current in tracking mode.

osc

refdv+1

ref

Phase

Detector

VCO

synr+1

vco

Loop Divider

1
2

cmp

VDDPLL

XFC Pin

vco

(

)

-----------------------

120

(

)

120

------------------------

= -97.43MHz/V

341.0Hz/

MC9S12DT128B Device User Guide -- V01.07

106

The loop bandwidth f

should be chosen to fulfill the Gardner's stability criteria by at least a factor of 10,

typical values are 50.

= 0.9 ensures a good transient response.

And finally the frequency relationship is defined as

With the above values the resistance can be calculated. The example is shown for a loop bandwidth
f

=11kHz:

The capacitance C

can now be calculated as:

The capacitance C

should be chosen in the range of:

A.5.3.2 Jitter Information

The basic functionality of the PLL is shown in

Figure A-2

. With each transition of the clock f

cmp

, the

deviation from the reference clock f

ref

is measured and input voltage to the VCO is adjusted

accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in

Figure A-3

ref

------------------------------------------

------

ref

4 10

--------------

0.9

(

)

;

< 25kHz

VCO

ref

-------------

synr

(

)

= 50

n f

-----------------------------

= 2*

*50*11kHz/(341.0Hz/

)

=10.1k

=~ 10k

----------------------

0.516

---------------

0.9

(

)

;

= 4.69nF =~ 4.7nF

= 470pF

MC9S12DT128B Device User Guide -- V01.07

108

This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the
effect of the jitter to a large extent.

Table A-16 PLL Characteristics

Conditions are shown in Table A-4 unless otherwise noted

Num C

Rating

Symbol

Min

Typ

Max

Unit

P Self Clock Mode frequency

SCM

5.5

MHz

D VCO locking range

VCO

MHz

Lock Detector transition from Acquisition to Tracking
mode

trk

NOTES

1. % deviation from target frequency

D Lock Detection

Lock

1.5

(1)

D Un-Lock Detection

unl

0.5

2.5

(1)

Lock Detector transition from Tracking to Acquisition
mode

unt

(1)

C PLLON Total Stabilization delay (Auto Mode)

2. f

REF

= 4MHz, f

BUS

= 25MHz equivalent f

VCO

= 50MHz: REFDV = #$03, SYNR = #$018, Cs = 4.7nF, Cp = 470pF, Rs =

10K

stab

0.5

D PLLON Acquisition mode stabilization delay

(2)

acq

0.3

D PLLON Tracking mode stabilization delay

(2)

0.2

D Fitting parameter VCO loop gain

-120

MHz/V

D Fitting parameter VCO loop frequency

MHz

D Charge pump current acquisition mode

| i

38.5

D Charge pump current tracking mode

| i

3.5

C Jitter fit parameter 1

(2)

1.1

C Jitter fit parameter 2

(2)

0.13

MC9S12DT128B Device User Guide -- V01.07

112

Figure A-6 SPI Master Timing (CPHA =1)

Table A-18 SPI Master Mode Timing Characteristics

NOTES

1. The numbers 7, 8 in the column labeled "Num" are missing. This has been done on purpose to be consistent between the

Master and the Slave timing shown in Table A-19.

Conditions are shown in Table A-4 unless otherwise noted, C

LOAD

= 200pF on all outputs

Num C

Rating

Symbol

Min

Typ

Max

Unit

P Operating Frequency

bus

P SCK Period t

sck

= 1./f

sck

2048

bus

D Enable Lead Time

lead

sck

D Enable Lag Time

lag

sck

D Clock (SCK) High or Low Time

wsck

bus

1024 t

bus

D Data Setup Time (Inputs)

D Data Hold Time (Inputs)

D Data Valid (after SCK Edge)

D Data Hold Time (Outputs)

D Rise Time Inputs and Outputs

D Fall Time Inputs and Outputs

SCK

(OUTPUT)

SCK

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

MSB IN

BIT 6 . . . 1

LSB IN

MASTER MSB OUT

MASTER LSB OUT

BIT 6 . . . 1

PORT DATA

(CPOL

PORT DATA

(OUTPUT)

1.If configured as output

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

MC9S12DT128B Device User Guide -- V01.07

114

Table A-19 SPI Slave Mode Timing Characteristics

Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs

Num C

Rating

Symbol

Min

Typ

Max

Unit

P Operating Frequency

bus

P SCK Period t

sck

= 1./f

sck

2048

bus

D Enable Lead Time

lead

cyc

D Enable Lag Time

lag

cyc

D Clock (SCK) High or Low Time

wsck

cyc

D Data Setup Time (Inputs)

D Data Hold Time (Inputs)

D Slave Access Time

cyc

D Slave MISO Disable Time

dis

cyc

D Data Valid (after SCK Edge)

D Data Hold Time (Outputs)

D Rise Time Inputs and Outputs

D Fall Time Inputs and Outputs

MC9S12DT128B Device User Guide -- V01.07

117

Table A-20 Expanded Bus Timing Characteristics

Conditions are shown in Table A-4 unless otherwise noted, C

LOAD

= 50pF

Num C

Rating

Symbol

Min

Typ

Max

Unit

P Frequency of operation (E-clock)

25.0

MHz

P Cycle time

cyc

D Pulse width, E low

D Pulse width, E high

D Address delay time

D Address valid time to E rise (PW

)

D Muxed address hold time

MAH

D Address hold to data valid

AHDS

D Data hold to address

DHA

D Read data setup time

DSR

D Read data hold time

DHR

D Write data delay time

DDW

D Write data hold time

DHW

D Write data setup time

(1)

(PW

DDW

)

DSW

D Address access time

(1)

cyc

DSR

)

ACCA

D E high access time

(1)

(PW

DSR

)

ACCE

D Non-multiplexed address delay time

NAD

D Non-muxed address valid to E rise (PW

NAD

)

NAV

D Non-multiplexed address hold time

NAH

D Chip select delay time

CSD

D Chip select access time

(1)

cyc

CSD

DSR

)

ACCS

D Chip select hold time

CSH

D Chip select negated time

CSN

D Read/write delay time

RWD

D Read/write valid time to E rise (PW

RWD

)

RWV

D Read/write hold time

RWH

D Low strobe delay time

LSD

D Low strobe valid time to E rise (PW

LSD

)

LSV

D Low strobe hold time

LSH

D NOACC strobe delay time

NOD

D NOACC valid time to E rise (PW

NOD

)

NOV

MC9S12DT128B Device User Guide -- V01.07

120

B.2 112-pin LQFP package

Figure 22-5 112-pin LQFP mechanical dimensions (case no. 987)

DIM

MIN

MAX

20.000 BSC

MILLIMETERS

10.000 BSC

20.000 BSC

10.000 BSC

---

1.600

0.050

0.150

1.350

1.450

0.270

0.370

0.450

0.750

0.270

0.330

0.650 BSC

0.090

0.170

0.500 REF

0.325 BSC

0.100

0.200

0.100

0.200

22.000 BSC

11.000 BSC

22.000 BSC

11.000 BSC

0.250 REF

1.000 REF

0.090

0.160

VIEW Y

L-M

0.20

4X 28 TIPS

PIN 1
IDENT

112

VIEW AB

0.10

0.050

SEATING
PLANE

GAGE PLANE

VIEW AB

(Z)

(Y)

(K)

0.25

VIEW Y

108X

SECTION J1-J1

BASE

ROTATED 90 COUNTERCLOCKWISE

METAL

L-M

0.13

1
2
3

L-M

0.20

112X

X=L, M OR N

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. DIMENSIONS IN MILLIMETERS.
3. DATUMS L, M AND N TO BE DETERMINED AT

SEATING PLANE, DATUM T.

4. DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE, DATUM T.

5. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B INCLUDE MOLD MISMATCH.

6. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE D
DIMENSION TO EXCEED 0.46.

MC9S12DT128B Device User Guide -- V01.07

121

B.3 80-pin QFP package

Figure 1 80-pin QFP Mechanical Dimensions (case no. 841B)

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF

LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC

BODY AT THE BOTTOM OF THE PARTING LINE.

4. DATUMS -A-, -B- AND -D- TO BE

DETERMINED AT DATUM PLANE -H-.

5. DIMENSIONS S AND V TO BE DETERMINED

AT SEATING PLANE -C-.

6. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B DO INCLUDE MOLD MISMATCH

AND ARE DETERMINED AT DATUM PLANE -H-.

7. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM

MATERIAL CONDITION. DAMBAR CANNOT
BE LOCATED ON THE LOWER RADIUS OR

THE FOOT.

SECTION B-B

DETAIL A

-A-

-D-

A-B

0.20

0.05 A-B

-B-

VIEW ROTATED 90

DETAIL A

-A-,-B-,-D-

DETAIL C

SEATING
PLANE

-C-

DATUM
PLANE

0.10

-H-

DATUM
PLANE

-H-

DETAIL C

DIM

MIN

MAX

MILLIMETERS

13.90

14.10

13.90

14.10

2.15

2.45

0.22

0.38

2.00

2.40

0.22

0.33

0.65 BSC

---

0.25

0.13

0.23

0.65

0.95

12.35 REF

0.13

0.17

0.325 BSC

0.13

0.30

16.95

17.45

0.13

---

16.95

17.45

0.35

0.45

1.6 REF

A-B

0.20

A-B

0.20

0.05

A-B

0.20

A-B

0.20

Document Outline

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Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S12MSCANV2D